daem
Newbie
Hi all!
Is there a way to ignore VHDL code during synthesis while using design_compiler? I'd want to add code to my design only for simulation purposes, and not have the synthesizer deal with it.
I have seen that some other synthesizers support this syntax:
But I have not been able to find if that is supported in the design_compiler docs (I'd imagine not).
Is there a way to ignore VHDL code during synthesis while using design_compiler? I'd want to add code to my design only for simulation purposes, and not have the synthesizer deal with it.
I have seen that some other synthesizers support this syntax:
Code:
-- synthesis translate_off
Code goes here
-- synthesis translate_on