[SOLVED] Ignoring code during synthesis using design_compiler

[daem]

Hi all!

Is there a way to ignore VHDL code during synthesis while using design_compiler? I'd want to add code to my design only for simulation purposes, and not have the synthesizer deal with it.

I have seen that some other synthesizers support this syntax:

-- synthesis translate_off
Code goes here
-- synthesis translate_on

But I have not been able to find if that is supported in the design_compiler docs (I'd imagine not).

 

[ThisIsNotSam]

try

-- RTL_SYNTHESIS OFF

or

-- pragma translate_off
-- pragma translate_on

 

[daem]

At the end I did try

−−synthesis translate off

and it worked, so I guess never assume anything with these tools.

I also tried all of @ThisIsNotSam's suggestions, and all of them worked, so thanks for the reply!