IGBT's getting hot at load using IR2113 driver

[Christianreyem]

Hello everyone
I am doing my final electrical engineering project. I am building an induction furnace using a full bridge IGBT inverter. I am using an IR2113 high/low driver as well as dual channel optocoupler for isolation purposes.

I have encounter a problem when testing the inverter at no-load. A large ringing occurs at the flat tops of my inverter output. At this stage my IGBT's do not get hot when running at no-load, but the ringing does prevent me from pushing higher voltage through my DC bus.

I implemented a C-snubber and found that the ringing went away the larger the capacitor over the emitter and collector of the IGBT's. What i noticed was when the ringing went done, the IGBT's became hotter even at no-load.

The yellow curve is the current measured through the conductor between my DC supply and the DC bus terminals on my inverter PCB. The blue again is my inverter output at no load. The yellow is a bit concerning seeing that no load is attached. I have significant amount of deadtime also implemented through my stm32. After presenting this problem to my study leader, he suggested that I implement a diode between my DC supply and DC bus on the inverter. I implemented it and found that the ringing at the my flattops disappeared.

Now my IGBT's get hot and the diode also starts to heat up. I don't want to push the DC voltage to much because the current increases with it(see yellow curve). I am lost as to what can be the cause for these losses being generated by the IGBT's. For additional information below is my gate to emitter voltage waveform and looks like there is no shoot through between the two complementary signals from the IR2113 and the optocoupler.

Any suggestions will be appreciated.
Thank you in advance.

 

[FvM]

Ringing is caused by excessive wiring inductance. Can you show a photo of inverter including position of DC-link capacitor?

 

[Easy peasy]

Jeeez, - get rid of the caps across the IGBT's, a snubber is an R and C, start with 4n7 and 100 ohm across each IGBT.

Set the Ron resistor to get about 100nS flat section in the Vgs turn on, and have a fast turn off - double check your dead time on the gate timing is at least 400nS

at least 400nS !

Show us the complete circuit - schematic and pictures ! we can't see any decoupling - nor how poor the layout is

 

[KlausST]

Hi,

I´m with EasyPeasy:
The schematic is not according IC manufacturer recommendations.
And I guess the PCB layout is neither.

So the problems are quite expectable.

The Semicondcutor manufacturers provide all informations you need, but you need to use them!
Read and follow:
* Datasheet
* application notes
* design notes
* other design informations and tools

***
All in all switch mode power supply design problems are one of the most often discussed problems here.
Often the problems are the same ... thus the answers are the same.

Klaus

 

[Christianreyem]

Here is a photo of the entire PCB layout. The red parts the capacitors over the IGBT's.

Easy peasy what is meant with the Ron resistor. Is it the gate resistor ?

Klaus the IR2113 and optocoupler circuits in my schematics are taken directly from their respective datasheets and application notes. Unless you are referring to some other part of the schematic that might look a bit wonky ?

 

[D.A.(Tony)Stewart]

When you suppress an inductive spike with an over down capacitor, you increase the Ic squared *(ESR and Rdson) in the active devices. Null your conductor traces 1nH/mm when you have very fast switching times. You can reduce your dead time to sub microseconds and just allow for thermal delays from PTC effects of RdsOn. As long as the spikes are well below Vds Max and the slew rates with a tiny loop area will minimize your EMI radiation.

Keep in mind, you will always have an RLC spike response, including your 10:1 probe Gnd length and probe capacitance. This will help you understand what you were seeing.

 

[KlausST]

Here is a photo of the entire PCB layout.

NO, this is not the entire PCB, since we need to see the back side, too.

The red parts the capacitors over the IGBT's.

Why didn´t you remove them ... as already told?

Why didn´t you add the decoupling capacitors .. as already told?

schematics are taken directly from their respective datasheets and application notes.

--> give links to the documents

 

[Christianreyem]

https://www.onsemi.com/download/data-sheet/pdf/hcpl2631-d.pdf
Optocoupler datasheet
https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d462533600a4015355c80333167e
Gate driver datasheet

https://www.farnell.com/datasheets/2254418.pdf

Gate driver application note

--- Updated Today at 12:18 PM ---

Oky so the capacitors are the reason for the IGBT's getting hot. What resistor and capacitor value range would be suitable. From the other responses I gather that the capacitor should be in the range of a couple of nano-farads. Is this correct in assuming ?

When you suppress an inductive spike with an over down capacitor, you increase the Ic squared *(ESR and Rdson) in the active devices. Null your conductor traces 1nH/mm when you have very fast switching times. You can reduce your dead time to sub microseconds and just allow for thermal delays from PTC effects of RdsOn. As long as the spikes are well below Vds Max and the slew rates with a tiny loop area will minimize your EMI radiation.

Keep in mind, you will always have an RLC spike response, including your 10:1 probe Gnd length and probe capacitance. This will help you understand what you were seeing.

 

[KlausST]

Hi,

Optocoupler:
Page 5 says:

1. The VCC supply to each optoisolator must be bypassed by a 0.1 F capacitor or larger. This can be either a ceramic or solid tantalum capacitor
with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device.

I don´t see this.

Gate driver datasheet says:

V_IH needs to be 9.5V minimum

What are your values? Not expected ... but true values

Gate driver AN says:

Local decoupling capacitors on the V CC
(and digital) supply are useful in practice to compensate for the inductance of the supply lines.

Connect decoupling capacitors directly across the appropriate pins as shown in Figure 7.

Indeed there are 7 locations where "decoupling capacitors are mentioned". I don´t see tham in your design.

There is a whole section about bootstrap components:
* They recommend non_electrolytic capacitors ... still "good" electrolytics can do the job. Did you select the correct ones?
* About bootstrap diode it says:

that this diode have an ultra-fast recovery to reduce the amount of charge that is fed back from the bootstrap capacitor into the supply.

The 1N400x are way too slow .... far from being "ultra fast"

there is a whole section:

6. LAYOUT AND OTHER GENERAL GUIDELINES

From what I see I doubt you followed all the rules.

****
There may be more issues...

Klaus

 

[D.A.(Tony)Stewart]

Judging by your photographs, I would say all your spikes are from capture errors on your probing faults. Instead, use a 10 to 1 probe , remove the tip and ground clip and use a coaxial spring as a Ground clip to go between signal and ground 1 cm apart. Use this method for a signals with spectrum above 20MHz = 0.35 / Tr (10~90%)