IF statement error in 8bitchecksum

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nvm

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Hello everyone,
I have been trying to implement a 8bit checksum in vhdl.
Here is my code for that

Code VHDL - [expand]
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library IEEE;
 
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity checksum is
port (
    sn : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
    dat : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
    sum  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
end checksum;
 
architecture Behavioral of checksum is
-- signals
signal sumwithcarry : std_logic_vector (8 downto 0); 
signal datapac1 : std_logic_vector(7 downto 0);
signal datapac2 : std_logic_vector(7 downto 0);
signal datapac3 : std_logic_vector (7 downto 0);
signal datapac4 : std_logic_vector (7 downto 0);
signal datapac5 : std_logic_vector (7 downto 0);
signal datapac6 : std_logic_vector (7 downto 0);
signal digit : std_logic;
begin
datapac1 <= sn(0) & sn(1) & sn(2) & sn(3) & sn(4) & sn(5) & sn(6) & sn(7);
datapac2 <= sn(8) & sn(9) & sn(10) & sn(11) & sn(12) & sn(13) & sn(14) & sn(15);
datapac3 <= sn(16) & sn(17) & sn(18) & sn(19) & sn(20) & sn(21) & sn(22) & sn(23);
datapac4 <= sn(24) & sn(25) & sn(26) & sn(27) & sn(28) & sn(29) & sn(30) & sn(31);
datapac5 <= dat(0) & dat(1) & dat(2) & dat(3) & dat(4) & dat(5) & dat(6) & dat(7);
datapac6 <= dat(8) & dat(9) & dat(10) & dat(11) & dat(12) & dat(13) & dat(14) & dat(15);
 
sumwithcarry <= "00000000" + datapac1 + datapac2 + datapac3 + datapac4 + datapac5 + datapac6;
digit <= sumwithcarry(8);
 
 
if (digit = '1')  then   --error here
sumwithcarry := '0' & sumwithcarry(7 downto 0) + '1';   --error here
end if;
 
 
sum <= sumwithcarry(7) & sumwithcarry(6) & sumwithcarry(5) & sumwithcarry(4) & sumwithcarry(3) & sumwithcarry(2) & sumwithcarry(1) & sumwithcarry(0);
 
end Behavioral;




But I keep getting these errors

Can someone help me fix it.
 
Last edited by a moderator:

if..then is only allowed in sequential code (a process)
can't use := for a signal
 
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    nvm

    Points: 2
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I did that. 

Code VHDL - [expand]
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process (digit)
if (digit = '1')  then   --error line
sumwithcarry <= '0' & sumwithcarry(7 downto 0) + '1';
end if;
end process;



I still end up with an error
Error: syntax error near if (VHDL-1261) C:\Users\orthodata\Desktop\IGLOO\ASIC PROJECT\First\hdl\checksum.vhd(55)
Click to expand...
 
Last edited by a moderator:

it should be
Code VHDL - [expand]
1

process (digit) begin


also you have a width problem with the following line as your assigning a 8-bit wide value to a 9-bit value.
Code VHDL - [expand]
1

sumwithcarry <= "00000000" + datapac1 + datapac2 + datapac3 + datapac4 + datapac5 + datapac6;

I also you shouldn't be assigning sumwithcarry outside the process that is assigning it too.

Others more familiar with VHDL will also probably chime in that you shouldn't be using std_logic_arith (synopsys extension) as it's been deprecated. There are IEEE packages which support addition using other types.

regards
 
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    nvm

    Points: 2
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I suggest a VHDL text book.

process statement part will be opened with "begin".
 
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    nvm

    Points: 2
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FvM said:
I suggest a VHDL text book.

process statement part will be opened with "begin".
Click to expand...

actually plan on buying one. any suggestions on that?

- - - Updated - - -


thank you. that helped me. but it didn't bother me with the width problem.
 

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