If setup time is met, so how hold time violation maybe occur

[khaila]

supposed cascaded two FFs, FF1 and FF2, thought combinational logic.
while
D1 <= X; X is the input of FF1.
D2 <= Q1 but throught comb logic.
Y <= Q2; Y is the output of FF2.
-----------------------
Relevant parameters for FF1:
Tcycle. Ts1, Th1, Tc2q1
For FF2:
Tcycle, Ts2, Th2, Tc2q2, Tp0 ; while Tp0 is the propagation time for the combinational logic.
--------------------------
Are the following equations for FF2 right???
Tcycle>Ts2+Tc2q2+Tp0
Th1<Tc2q1+Tp0

Please check me!
Supposed the upon equations are right, so how hold time violation in FF2 may occur???
You see that if Setup time is met in FF2 then Hold time is necessarily met.

Please advice me!!!

 

[eeeraghu]

Re: If setup time is met, so how hold time violation maybe o

Also depends on the +/-ve Clock skew.