If pll loop is open,why vco output eye diagram is closed?

[eejli]

Hi guys,

I have a on-chip PLL runing at open loop configuration,i.e., I broke the loop filter from the loop.

And I just let the input of vco be connected to the board via a pin so that I can adjust the vco output frequency from the board.

If I plug the vco output to a scope and see its eye, I found in the open loop configuration the eye get close without any opening. Can some body explain a little bit for me?

My understanding is that though in the open loop the vco phase noise can be accumulated over time and close the eye. Why in the close loop case the jitter is not accumulated to close the eye diagram.

Thanks!

 

[AdvaRes]

The PLL is a looped system that adjusts dynamicalcy the VCO output frequency and keep it as stable as possible that's why you get a open eye diag. In a open loop even if its control voltage is maintained stable the output frequency of the VCO will vary resulting in a closed eye diag.