If a layout uses Q random walk can INL and DNL be <1 LSB?

[yen]

INL and DNL question

Dear all,
I am doing 12-bits dac. I simulation dac in hspice about FF,TT,FS,SF and SS.
But DNL and INL are bigger than 1LSB in FF and SS.(about 2LSB)
I have a question. If my layout use Q² random walk,can my INL and DNL be smaller than 1 LSB?Thanks.
Beside FF,TT,FS,SF and SS, what should I run in hspice?

 

[tuza2000]

INL and DNL question

is there any glitch in your design?
i think your inl and dnl will not smaller than 1lsb use Q² random walk
regards

 

[jiangwp]

Re: INL and DNL question

First, i want to know how you can simulate and measure the INL and DNL of dac.

If you use the behavior model, i think the INL and DNL can get, otherwise , i think the result is doublt.

The INL and DNL of DAC is static parameter, only the chip is fabricated, the parameter is meanful. They charactize the mismatch of transistor about the fabricate.

 

[SkyHigh]

Re: INL and DNL question

yen,

can my INL and DNL be smaller than 1 L

You can achieve INL and DNL less than +/- 1 bit, in fact you should make it less than +/- 0.5 LSB, else your cannot achieve monotonicity and eliminate missing codes.

1. You can design 14-bit resolution instead of 12-bit, thus likely to get 12-bit accuracy.

2. If you are using weighted capacitors or charge redistribution network in DAC, try to use big capacitors to reduce percentage matching error due to dimensions.

3. Use 0.5, 0.35 or 0.25 instead of 0.18 or 0.13 to avoid matching error and difficulty due to shorter gate length.

4. Improve your bandgap reference for Vref. This is the most important sub-circuit in DAC and ADC.

 

[neter]

Re: INL and DNL question

Hi,yen

Can you tell me how to do simulation INL and DNL on dac in hspice ?

How to do setting simulation condition parameter in hspice?

Can you post or e-mail example to me?

I am doing 8-bit current-steering DAC.

Thank you very much,yen.

Neter

 

[yen]

Re: INL and DNL question

Hi,yen

Can you tell me how to do simulation INL and DNL on dac in hspice ?

How to do setting simulation condition parameter in hspice?

Can you post or e-mail example to me?

I am doing 8-bit current-steering DAC.

Thank you very much,yen.

Neter

Your inputs are pulse signals.
Then read your output data.
Maybe you can use Matlab to manage your data.
After this,your can get INL and DNL.

 

[neter]

Re: INL and DNL question

neter wrote:
Hi,yen

Can you tell me how to do simulation INL and DNL on dac in hspice ?

How to do setting simulation condition parameter in hspice?

Can you post or e-mail example to me?

I am doing 8-bit current-steering DAC.

Thank you very much,yen.

Neter

yeb write:
Your inputs are pulse signals.
Then read your output data.
Maybe you can use Matlab to manage your data.
After this,your can get INL and DNL.


Hi,yen

Can you tell me about deltail matlab algorithm code or example code in simulation INL and DNL method?

Thank youvery much.

 

[zenisle]

Re: INL and DNL question

inl should greater dnl in common.

 

[schwang1970]

Re: INL and DNL question

To simulate INL and DNL by Hspice and Specture is hard and waste time.Ususlly simulate the converter's FFT is another economic method.

 

[yen]

Re: INL and DNL question

To simulate INL and DNL by Hspice and Specture is hard and waste time.Ususlly simulate the converter's FFT is another economic method.

Dear schwang1970,
I try use simulink to do A/D. I generate my inputs. But my inputs are 0 or 1.
They are not regular.How do I do that my inputs connected my 12 bits D/A.
And how do I do FFt? I have write fft code in matlab? Can you tell me detail?
Or give me a example. Thanks very much.