IEE 754 Floating Point addition

[oAwad]

IEEE 754 Floating Point addition

Given that one of the two operands in an IEEE 754 single-precision FP addition has no mantissa (just a power of 2), how can this help optimize the addition operation on the hardware level?

 

[KlausST]

Hi,

What do you mean with "has no mantissa"?
I can't see how this can be.

Give an example.

Klaus

 

[oAwad]

As I said, one of the 2 operands is just a power of 2 (its mantissa is always zero), e.g. 1.101101x2^5 + 2^3
How can such assumption help optimize the architecture of the FP adder unit (reduce the cost of alignment, normalization, or addition)? Thanks

 

[barry]

As I said, one of the 2 operands is just a power of 2 (its mantissa is always zero), e.g. 1.101101x2^5 + 2^3
How can such assumption help optimize the architecture of the FP adder unit (reduce the cost of alignment, normalization, or addition)? Thanks

You still have to do floating point addition since ONE of your numbers has a non-zero mantissa. What I think really happens is that your summation becomes:

1.101101 x 2^5 + .01 x 2^5

 

[KlausST]

Hi,

I was confused... since mathematically: if the mantissa is zero, then the whole result is zero.

But float values show only the fractional part of the a mantissa with the integer part to be "1".

So indeed the case you want to talk about is: when fractional_part_of_the_mantissa is zero and thus the mantissa is "1".

I agree with barry. But even the example is confusing since some numbers are shown as binary values (blue) while others are shown as decimal values (green):

1.101101 x 2^5 + 0.01 x 2^5

Klaus

 

[barry]

I think part of the problem here is terminology. Mantissa can have two very different meanings. The OP is taking it to mean the value after the decimal point. In IEEE 754, and most discussions of floating point, it means the SIGNIFICAND, the signicant number of digits in the non-exponent part. Floating point does NOT have any fractional part. The significand(mantissa) is an integer. That's why Klaus is correct in assuming OP's "zero mantissa" number is zero. OP should read about IEEE 754.

 

[KlausST]

Hi,

Not to provide even more confusion, I recommend the OP should give a more suitable example.
Either all as decimals, or all as binary, or each value labelled what numbering system it is.

Klaus

 

[FvM]

Although not completely clear, the example given in post #3 1.101101x2^5 + 2^3 suggests that the OP well understands the IEEE coding and that "no mantissa" can be translated to all mantissa bits zero, or 1.101101x2^5 + 1.00000x2^3

how can this help optimize the addition operation on the hardware level?

My guess is: Not at all if you allow arbitrary exponent values for both summands.

 

[oAwad]

My guess is: Not at all if you allow arbitrary exponent values for both summands.

Thanks for your reply. Constraining the exponent values can obviously eliminate/reduce the alignment of the summands, but do you think there is a way to reduce the width of the adder (given that one of the summands has only one bit as '1')?

 

[FvM]

After normalization, the one 1 can be shifted to any mantissa position.