[Idea] Re-use the waveform (.vcd)...

vsim vcd

***** M0delsim *****
-- Provide a way to resimulate with the VCD file:
---- step 1: Dump the VCD file during the 1st simulation;
VSIM 1> vcd dumpports -file verilog.vcd /test_top/dut/*
VSIM 2> run
VSIM 3> quit
----step 2: Simulate again (without original test bench).
VSIM 1> vsim -vcdstim verilog.vcd top
VSIM 2> run

***** VC$ *****
-- Provide an utility to generate the testbench from VCD file:
----Limitation: DO NOT allow bi-directional port(s) ....
----step 1: Prepare the configuration file vgen.cfg
----step 2: > vcat verilog.vcd -vgen

***** NC-Veril0g *****
-- Have not found similar feature ???
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ps:
Related topic **broken link removed**
"Question: .wlf -> .vcd ?"