I have no doubt it will look "okay" in simulation. This sort of thing always looks pretty in simulation. ;-)
The problems start when you implement it in real hardware. As ads_ee pointed out, you will have clock skew to deal with. Because some of your logic is fed with CLK, and some logic is fed with the inverted CLK. And since we are now talking about real hardware, where does this inverted clock come from? That will depend on the fpga you're working...
Say on for example you are using a spartan-3. That means you will have to do the clock inversion with a DCM, and you will have to use up an extra global clock net. Global clock nets are a relatively scarce resource, so you don't want to use them for every little thing. Apart from the use of a global clock net you now have quite a bit of skew to deal with. That inverted clock is a newly generated clock signal and will have associated jitter (clock uncertaintly). That jitter will have to be taken into account during timing constraints. Short version: this jitter will effectively lower the maximum frequency you can reliably run on.
For a spartan-6 things are a little better. You have local clock inversion, which means that you route only 1 clock signal (CLK). Then whenever you need the inverted version there's a tiny bit of dedicated hardware that inverts the clock signal on the spot. You can read the datasheet for more details... The good news is that you now only need 1 clock net instead of 2. The bad news is that you still get all sorts of challenges. Becaaaaaaaause your clock signal will not have a perfect 50% duty cycle. And because of that you get timing mismatches between CLK and NOT CLK. Essentially the same problem as with the jitter example earlier on. And as such in reality you will get a lower running frequency than you would have for a perfect 50% duty cycle.
So I am not saying it cannot be done. Because ... it can be done. But it does require more work to setup the constraints carefully to make sure that it will work reliably. And you may not be gaining any advantages over the regular boring 1 clock only case without inversions. So what is the design goal here? Just having fun and seeing if it can be done? In which case have at it! Try to get to run it near the rated max clock of your chosen fpga, and then double that by doing it the DDR way. That way you'll get to see all the fun stuff that can go wrong.
If you want something that "just works" then generating a X2 clock and using that is a lot safer. And not in the least because the synthesis and place & route tools have been optimized for the sort of circuit with a boring single clock. As soon as you stray from the synchronous logic path you will have to do more thinking yourself to make sure things don't go wrong.
You say you just started out with VHDL. If you currently have some spare time to look into how to properly constrain a design, I would say go for it. You'll learn lots of handy stuff.