IC power supply backup

[FreshmanNewbie]

I'm using this ic

The datasheet for the 23LVC1024 SRAM specifies a minimum supply voltage of 2.5V. I want to use a power supply set at 2.5V, but with tolerance that could be less than that, say down to 2.4V. That implies that I could not use this part with the supply that I have designed. However, there is a VTRIP (typically 1.8V) at which the chip switches over to the VBAT supply. This implies that the part will work at some voltages below 2.5V, but I need to know that operation is guaranteed. Can you tell me what happens to the functionality of the part between VCC = 2.5V and VTRIP?

Also shall I connect my 2.5V supply to both Vcc and Vbat pins? Or how it should be connected?

 

[KlausST]

Hi,

It´s rather clear. The datasheet gives all informations you need.
It´s the most reliable source of information.

It clearly states minimum supply for operation is 2.5V.

It also clearly states:

If the V BAT function is not being used, it is recommended to connect this pin to VSS.

You may do whatever you want with this device. But if it fails
(on a different device, at different temperature, after some time, at differnt SPI clock frequency...)
it´s on you.



### fake information alert ON:
Lets imagine a random person writes this:

I`ve used this device and tested it at 2.3V supply. It works fine.

Also I used the device with VBat pin left unconnected. It works fine.

### fake information alert OFF:

Would you really rather rely on the "random person" information than on the datasheet information.

Back to VBat:
Your question implies that you don´t need backup functionality. So whay did you choose this device and not a standard SPI SRAM (like the cheaper 23LC1024)?

Klaus

 

[FreshmanNewbie]

Hi,

It´s rather clear. The datasheet gives all informations you need.
It´s the most reliable source of information.

It clearly states minimum supply for operation is 2.5V.

It also clearly states:

You may do whatever you want with this device. But if it fails
(on a different device, at different temperature, after some time, at differnt SPI clock frequency...)
it´s on you.



### fake information alert ON:
Lets imagine a random person writes this:

### fake information alert OFF:

Would you really rather rely on the "random person" information than on the datasheet information.

Back to VBat:
Your question implies that you don´t need backup functionality. So whay did you choose this device and not a standard SPI SRAM (like the cheaper 23LC1024)?

Klaus

The chart on page 15 of the data sheet also makes a claim that the Read/Write access operates with Vcc down to the Vtrip level. However this does seem to contradict the basic Vcc spec minimum of 2.5V. Since there does seem to be a "grey area" . Could you clarify

 

[KlausST]

Hi,

for sure there is a grey area.

You can test it with your own test conditions. And for sure the manufacturer will have added some headroom for their limits. It can be expected that a device still works "a bit beyond the specified limits", but c it can´t be guaranteed.

You may test beyond 20MHz, you may test beyond 85°C, you may test below 2.5V.

To the chart of page 15:
It does not contradict of what I have already written: It may work.
But you still can not be sure that it keeps all specified limits under all operation conditions.

Maybe it becomes slower and you can´t use it on 20MHz but it´s good up to 15MHz.
We simply can not know, because the datsheet does not tell.

And for me - because I try to design highly reliable devices - there is just one conclusion: It´s not reliable, thus I don´t use it.
But it´s my way. It´s all fine if you go your own way.
And for sure it´s a decision about the expectable risk. Can it cause a brake failure in my car ... or may it cause a reboot of my (home automated) TV ambient light.

I don´t want to force you to do it this or the other way. I just tell you my opinion.

Klaus

 

[FvM]

I agree that device operation in the range between Vtrip and Vccmin isn't exactly specified. But why are you asking? Do you say, I don't know what my system will be doing in this voltage range but I want the SRAM to safely keep the memory content though? If so, that's the wrong designer approach.

I would expect this: SRAM might perform memory accesses below Vccmin, but isn't guaranteed to operate correctly, e.g. keep the timing specifications. Therefore memory accesses should be blocked by the processor below Vccmin to avoid misinterpreted commands that might result in memory corruption. A power supply monitor resetting the processor or at least gating SRAM nCS below Vccmin would be a reliable method.