IC design for Powermos driver

[gilbertomaldito]

How to design an integrated PowerMos Driver.... My powerMOS cgs is quite large...(IRF730). Please help me how to design this properly.

For my initial design, I used inverter buffers with increasing sizes from
(first inverter) m=1,
2nd inverter : m=3,
3rd m=9,
4th m=81,
m=246, and so on. My W/L is 8u/2.5u for PMOS and 4u/2.5u for NMOS.
But my gate signal still not perfect, the time when it must be fully 10v, half of the time it stays in 6V. ex. for ton=2us , gate voltage must be 10v for 2us, but before it reaches 10v, voltage stays at 6v for 1us or worse. This is so abnormal.

I dont know if this is something about the driver or about the Buck topology.
But I just feel it is about the buffer.

 

[dick_freebird]

A switching plateau at mid-span comes from the MOSFET
Miller charge as the drain begins to swing. This says you need
a lot less output on-resistance in the driver, to plow through
that quickly.

Some applications will put an explicit gate resistor between
driver and MOSFET to control the drain slew rate. But this
says you need to drive down the driver resistance further,
so that the invariant external resistor dominates the sum and
sets the drain dV/dt to a fairly constant value.

You may want to look at the datasheets for FET drivers
from International Rectifier, Intersil, Micrel, et al to get a
feel for what kind of peak output current, output on resistance
(as VOL, VOH @ load) is commonly desired. Note that some
drivers will be said to drive a "Size X" FET, and you'd have
to determine what yours is.

Switching plateaus can also result from shoot-through
in the driver and predriver totem poles. Phasing the stages
of the taper chain for asymmetric switching can cut the
shoot-through current substantially and improve output
transition times (though raw delay, you can't do much
about, that element is not often as important; transition
time goes directly to power dissipation in the driver and the
driven FET.

 

[frankliner]

Generally external FET drivers are capable of ~1A.

 

[erikl]

For my initial design, I used inverter buffers with increasing sizes from
(first inverter) m=1,
2nd inverter : m=3,
3rd m=9,
4th m=81,
m=246, and so on.

I think for geometrical factor 3 scaling the series should be 1 3 9 27 81 243 ...

 

[ND700]

how about using geom factor 6-10 instead of 3

Added after 9 minutes:

that miller plateau region (flat region) in gate signal is caused by gate current charging Cgd. In this region, Vgs keeps constant and gate current discharges Cgd and Vds decreases. After Vds drops below Vgs-Vth, MOS enters the linear region, then, Vgs increases again.

If you put source inductance Ls at the source node of MOS, the miller plateau region will be even longer, because Ids induced voltage across Ls reduces the gate current.

 

[gilbertomaldito]

I am sorry about the (m) sizes, I just missed to write m=27, but I did follow the geom factor of 3.

SInce you also mentioned about this Geom factor... how can I get rid of this miller plateau region? because I experience this in my hspice simulation using IRF730 as my Power Mos. But in board level, actual implementation of design, the gate signal is perfectly square. I cannot even see the miller plateau effect.

If I will increase my m to 729 , will this be a big help?

I think I heard/read somewhere, I need to put a small resistance bet the output of tapper buffer and gate of power mos? is this true? ANy theoretical explanation about this?

 

[erikl]

... I just missed to write m=27, but I did follow the geom factor of 3.

Ok. But actually it's not important to follow this geometrical factor so accurately: you could also use series like 1 3 10 30 100 300 ... so you have simpler numbers.

I think I heard/read somewhere, I need to put a small resistance bet the output of tapper buffer and gate of power mos? is this true? ANy theoretical explanation about this?

I think this is just a safety precaution in order not to overload the prebuffer due to the initial high inrush current when loading/unloading the gate (+miller) cap. The prebuffer, however, limits its output current anyway. Another purpose is the insertion of a first-order low-pass filter (together with the gate+miller cap), which suppresses unwanted RF noise and also prevents spurious oscillation tendency.

BTW: The flat plateau region (in your HSPICE simulation) could possible also arise from high cross-current during the switching time when both inverter transistors are "ON" (what dick_freebird mentioned above as "shoot-through in the driver and predriver totem poles"). During this time span, the lion's share of the available predriver current is short-circuited through the totem-pole and is not available to further load/unload the following gates - by this creating the plateau.
You could perhaps detect this by separately monitoring the currents through both predriver transistors, and the gate current to the following stage.

 

[gilbertomaldito]

I read from another related topic:

the step in the gate voltage is due to the miller-effect talked about earlier in this post.

This is a common mistake in driving MOSfets, you do not calculate with the Cgs capacitance to determine the switching time (and so current needed). The Cgd contributs more to the actual switching time than the Cgs.

Switch on cycle :

1. When the gate driver switched on, you start charging the Cgs capacitance, nothing happens yet to the Vds until the Vth of the FET is reached.

2. When the Vds of the MOSfet starts to change (the beginning of the switching), you need to change the voltage on the Cgd capacitance from about the Vds to -Vth. This because Vds = Vdg + Vgs (the voltage on Cgs + the voltage on Cgd = Vds)
The rate Vds going down ONLY depends on how fast you can discharge the Cgd-capacitor! This energy (current) comes entirely from your gate drive circuit, so the more current you supply to the gate, the faster Cgd discharges, the faster Vds goes down, and the faster the switching takes place.

3. When the switching is over (Vds ~ 0V), you only charge Cgs to a higher voltage.

That's why the manufacturers of MOSFets give curves with 'total gate charge', and this on different Vds levels, because the importand parameters are Vds and Cgd. Since Cgd is voltage depended on its own, it is generally not enough to use only a single capacitance value.

So you can compare the switching time with the duration of the plateau on the gate voltage. Doubling the current, will double the switching speed.

For number 2.
I just know that I can increase the current by adding a larger taper buffer. But it seems it still couldnt charge Cgd that fast. Is there something wrong with by taper buffer? I still couldnt solve my stepping. The problem worsens especially during high frequency switching.At high freq, stepping at 6v stays longer than my gate input of 10v. [/quote]

 

[dick_freebird]

Some MOSFETs have application limits on drain dV/dt
(because drain-body capacitance pushes current into the
base of the parasitic BJT, and body local resistance can only
shunt away so much before waking up). The resistor,
against
Cgd*dV/dt, "pulls back" some Vgs to soften the ramp for
safety in this respect.

You are seeing the result of such a resistance, only it is the
on-resistance of the driving FET (presuming you don not also
have totem pole shoot-through worsening things).

You probably should test your driver with both a realistic
power MOSFET model (which will show you the Miller push-back)
and a plain capacitance of roughly-right magnitude. If you
see the plateau in both cases, that's got to be shoot-through
while if it only appears in the FET-loaded case that is more about
the Miller action (cap to stiff ground, would only show a linear
leisurely transition).

The effective capacitance at the load is not just FET Cgs. The
drain capacitance is also significant, and its contribution
depends on drain voltage swing. Your FET manufacturer
probably specs Cgg (total gate charge) as well as Cgs.

Qgg=Cgs*(Vgs2-Vgs1)+Cgd*(Vdg2-Vdg1)
Cgg=Qgg/(Vgs2-Vgs1)

Taper strategies vary depending on what you want to achieve.
Low power wants higher taper factors (to a point) and high
speed / fast transition wants a low taper factor.

Look at the final stage. There should be no cross-conduction
at all, across the design-space. My first power MOSFET
driver design was interesting. I put an E-B diode where I
should have put a C-B diode (bipolar technology, back in
the day) and this led to a fat shoot-through pulse. I was
peering through the probe station microscope trying to deduce
why the parts were not passing, saw a glowing spot and
felt things hitting me in the face. The shoot-through current
was launching a silicon ballast resistor out of its dielectric
tub. Nice.

The output stage wants some kind of anti-shoot-through
timing. This can be "ballistic" or it can be designed with
a cross-lockout logic (the latter probably making it slower,
but more certain across PVT). This may extend a stage
or three back into the output stage, until you get to diminishing
return in terms of dynamic supply current. At each stage
th charge delivered to the next, ought to be >10X the charge
shot through to the "inactive" rail. Mobetta.

The last design I did (integrated buck) I used asymmetric
taper with the "turn off" devices at 1/2 and the "turn on"
devices 1/4 the gate width of the driven FET, abd the high
side & low side had 8 stage predrive chains that were
independent and tuned for a nonoverlap final result.

 

[gilbertomaldito]

Very informative... thanks D***-free****

I will try to follow your suggestions.