In a system, there are three possible I3C Bus Configurations:
1. Pure Bus: Only I3C Devices are present on the Bus.
2. Mixed Fast Bus: Both I3C Devices and Legacy I2C Devices are present on the Bus, such that the Legacy I2C Devices are restricted to ones that are generally permissible (i.e., Target-only, and no Target clock stretching), and that have a true I2C 50 ns Spike Filter on SCL. (I.e., I2C Devices that do not ‘see’ the SCL line as High when the High duration is less than 50 ns, across all temperatures and processes.)
3. Mixed Slow/Limited Bus: Both I3C Devices and Legacy I2C Devices are present on the Bus, such 1238 that the Legacy I2C Devices are restricted to ones that are generally permissible (i.e., Target-only, and no Target clock stretching), but that do not have a true I2C 50 ns Spike Filter on SCL.