I2C Slave - filters and clock.

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I want to implement a I2C SLAVE in an FPGA, just for learning purposes. I read in the I2C specification that for the FAST mode there is a timing parameter tSP = 50ns (max) which means "pulse width of spikes that must be suppressed by the input filter". Should this be a digital filter inside the slave? If yes, does that mean my slave must have a maximum clock period of 25ns (or something)?

Another question would be: is there a (robust) way of implementing this slave using the SCL line as the only clock? Or a faster second clock is needed (and in this case I would treat the SCL line as "data")? If so, how do I calculate the minimum frequency of this other clock?

Thanks in advance!
 
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I don't think you want to put a digital filter on a simple I2C interface; just an RC and proper design should suffice. And, if this is just for learning purposes, I wouldn't even worry about filtering out spikes that may not even exist.

I SUPPOSE you could use SCL as your main clock, but I wouldn't. That puts you at the mercy of whatever is driving SCL. If that device fails, your whole system fails.
 
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A full featured I2C slave supports clock stretching and implements SCL as bidirectional signal, surely not data. Even a simplified slave performs actions on SCL and SDA edges and can't use SCL as clock.

Most slave implementations on complex devices uses synchronous logic with overclocking, simple devices have asynchronous logic.
 
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FvM said:
A full featured I2C slave supports clock stretching and implements SCL as bidirectional signal, surely not data.
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Hi! Thanks! Why do you mean by "surely not data"?
--- Updated ---

FvM said:
Most slave implementations on complex devices uses synchronous logic with overclocking, simple devices have asynchronous logic.
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By asynchronous logic do you mean I2C slaves without a clock at all? Can't imagine...
 
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Lívia_Reis said:
Hi! Thanks! Why do you mean by "surely not data"?
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My fault, just confused. Commenting your post #1, I meant to say surely data not clock.
Lívia_Reis said:
By asynchronous logic do you mean I2C slaves without a clock at all? Can't imagine...
Click to expand...
Presume simple peripherals, e.g. I2C port expanders are implemented this way.
 
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