Hi,
When a device wants to transmit data, it typically checks the SDA line to see if it is currently pulled low
Indeed I guess one can say that both the MASTER as well as SLAVE check both SCL as well as SDA all the time.
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It´s all decribed in the specification. Please refer to it!
Post a timing diagram (idle, start, addressing... ) and we can discuss about it!
In short:
When a MASTER wants to transmit: (in timeline order)
* it first needs to wait for BUS_IDLE, which is both SCL and SDA = HIGH.
* Then the MASTER generates the START condition (1)
* then the MASTER sends out slave address (1) (7 bits Slave address + 1 bit READ/WRITE)
(All three states belong to the arbitration process)
* after this the SLAVE ACKnowledges with a LOW bit.
(1) it reads in the SDA line all the time. And it loses arbitration when it READS LOW, while it releases the bus (expecting HIGH)
This happens almost immediately. (Almost = because of noise filters)
Klaus