[General] I2C arbitration at edge or level of SCL

[yuhiub90]

Guys,

On I2C bus, if 2 masters issue START signal at almost the same time, bus arbitration must be performed. With respect to 1 SCL pulse of arbitration, I'm wondering where the process is taking place, only at edge of SCL or the whole HIGH duty cycle of SCL pulse?

Thanks

 

[yuhiub90]

I2C controller: edge or level trigger design?

Guys,

With I2C interface design, which design style should be used: edge (flop) or level trigger (latch) based. I see no restriction in I2C specs, latch based design could work fine.

Thanks

 

[Kurenai_ryu]

the i2c protocol states that SDA changes should be when SCL is low and it shouldn't change when SCL is high (except START and STOP right?) you can change SDA just right after the SCL falling edge, but you better read SDA in the middle of the SCL pulse, but to implement arbitration, you should read the SDA just after the rising edge of SCL, if SDA is low when your master tried sending high, then your master lost the arbitration, and should change to slave (with half the data recieved) or wait the STOP condition...

 

[yuhiub90]

What happens if SDA changes after rising edge of SCL during arbitration process. I mean at rising edge of SCL, both SDA of 2 master are HIGH, so both win the arbitration, but master 1 issues RESTART signal, and master 2 continues transferring data bit. Which master will win the arbitration?

 

[Kurenai_ryu]

of course master 2 should always check for a RESTART condition, the arbitration process is checked on every bit until the stop, not only on the first bit...

 

[yuhiub90]

of course master 2 should always check for a RESTART condition, the arbitration process is checked on every bit until the stop, not only on the first bit...

I know. But which master will win owning the bus in such case?

 

[FvM]

The restart wins, according to I2C specification:

Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level.