I2C 50ns spike suppression

[ebuddy]

spike surpression

I2C standard requires that spikes of 50 ns or shorter on SDL and SCL lines shall be suppressed. What kind of spike should I assume? Without any further details from the I2C spec, it seems that we have to design the circuit so that it supresses 50ns square wave swing between gnd to vdd (which I believe is the worst case). But it requires quite strong filter and this filter will distort the normal signals pretty heavily. Considering the reson for this feature is to mainly deal with the spike caused by the cross talk between SDL and SCL, what sort of spike shall we reasonabley assume in pratice?

The design I am working on is an asynchronous I2C interface (without high-speed sampling clock), so the spike suppression has to be done in analog circuit.

Thanks.

 

[FvM]

i2c crosstalk

Yes, square wave seems reasonable. NXP/Philips is specifying even 100 ns tolerated spike with their asynchronous chips.

If you apply the filtering after an input buffer, the timing should be almost independant of the spike waveform. This seems recommended anyway to avoid additional capacitive loading of the bus.

 

[Petre Petrov]

spike suppression

What is the speed and the configuration of your I2C implementation?
Also it depends on the involved ICs.
Sometimes a simple Low pass RC filter will do the job,
because the pulses are suppressed below the level of detection by the receivers.


Ref:
https://www.cs.unc.edu/Research/stc/FAQs/Interfaces/I2C-BusSpec-V2.1.pdf
THE I 2C-BUS SPECIFICATION, VERSION 2.1, JANUARY 2000