I want to synthesize my design without optimization in design compiler

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mostafa272

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Hi

I wrote verilog code for my design in gate level,but when I try to synthesize it with Synopsys Design Compiler, it changes my design automatically for optimization,but I don't like to change my design. I want to synthesize exactly what I wrote. Is there any way to force it to synthesize my design without any changes?
 

well if you write a gate level netlist you have to map it to the library cells which you are using. The whole idea of writing a behavioral code is that the gate level is generated by DC which can be optimized. Anyway you can always use don't_touch command on all the gates and the tool will not change those gates. I am not sure why you would want to do that?
 
I have to agree with artmalik. Why don't you want optimization? Do you want it to work worse than it could? Use don't_touch or keep if you must, but you should have a good reason.
 
My design is a low power multiplier. Previous jobs were simulated with HSPICE,but implementation of a big circuit in a spice netlist is not easy for me. so I want to synthesize previous designs and my design with powerful ASIC tool like design compiler. when I try to synthesize previous jobs, it optimizes their designs,but my design is synthesized without any changes. I expect to reduce the power dissipation,but it doesn't happen.
 

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