I/P reference clk and feedback clk offset in PLL

[SRIDHARAN619]

HI all ,

i have designed PLL. After locking input reference clk and feedback clk offset is in 2nm. how can i minimized this offset into some ps range. ref freq is 10MHz and o/p freq is 40MHz. and how can i identify problem behid this issue?

 

[leo_o2]

Offset is 2nS? This offset is found in simulation or measurement?

 

[SRIDHARAN619]

Yes, Offset is 2nS This offset is found in simulation.