I/O lines for LFEC20 DQ/DQS signal pairing

[davorin]

LFEC20 DDR signals

Someone knows which 16 IO lines they mean when talking about DQ/DQS signal pairing?

For the LatticeECP/EC devices, there is one dedicated DQS pin for every 16 I/Os. Any eight of these
I/O can be used to assign the DQ data pins. The ninth I/O of this group of 16 I/Os is the dedicated DQS pin.

So I assume the groups for bank 0 are:

PT10A ... PT17B
PT18A ... PT25B
PT26A ... PT33b

 

[lucbra]

Re: LFEC20 DDR signals

Kind of confusing, isn't it?
If you look at the pinout info for the EC20, I found following info

LDQS6, 19, 28, 36, 45 -> Pads PL6, PL19, 28, 36 and 45
BDQS6, 14, 22, 30, 38, 46, 54 -> pads PB6, etc.
RDQS6, 19, 28, 36, 45 -> Pads PR6, ...
TDQS6, 14, 22, 30, 38, 46, 54 -> pads PT6 ..

Every ninth I/O should be every ninth pad (like PL2A, PL2B, PL3A, ...)
note that L, B, R, T stands for Left, Right, Bottom and Top


I hope this explains a lot.