I need to design 2 counters please help!!!

[RaulitoESP]

I need to design 2 counters:

- a 2-bit counter that counts 2, 1, 0, 2, 1, 0 … (If the counter happens to be in state 3 in the beginning, it must first go to zero: 3, 0, 2, 1, 0, 2, 1, 0 …)

- a 3-bit counter that counts 7, 5, 1, 0, 7, 5, 1, 0 … (If the counter happens to be in state 2, 3, 4 or 6 in the beginning, it must first go to zero, e.g.: 2, 0, 7, 5, 1, 0, 7, 5, 1, 0 …)

Thank you a lot guys!

 

[ee171]

module counter2 (input clk, output [1:0] cnt_o);

reg [1:0] cnt_r, cnt_w;

assign cnt_o = cnt_r;

always@(*)
if(cnt_r==2'd3) cnt_w = 2'd0;
else if( cnt_r==2'd0) cnt_w <= 2'd2;
else cnt_w = cnt_r - 1'b1;

always@(posedge clk)
cnt_r <= cnt_w;

endmodule

module counter3 (input clk, output [1:0] cnt_o);

reg [2:0] cnt_r, cnt_w;

assign cnt_o = cnt_r;

always@(*)

case(cnt_r)
3'd7 : cnt_w = 3'd5;
3'd5 : cnt_w = 3'd1;
3'd1 : cnt_w = 3'd0;
3'd0 : cnt_w = 3'd7;
default: cnt_w = 3'd0;
endcase

always@(posedge clk)
cnt_r <= cnt_w;

endmodule

 

[RaulitoESP]

thank you! but i need also graphical design like circuits

 

[ee171]

if you copy and paste that code into any of the verilog program it will synthesis to a graphical diagram. Or you can just draw state-diagram with bits and logically performs on the state-bit for transitions.

 

[RaulitoESP]

thank you very much bro! respect!