I need some help with a calculator in vhdl

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Im really new in all about programing in vhdl so please describe your answers.
my teacher ask me to do a calc that can solve multiplication, sums, subtractions and compare between 2 number of 2 bits and be displayed in a 7 segment display.
I did this program and only gives me 3 errors saying that CASE statement is missing 6551 choices. i dont know what to do with that i need help please!!!

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
use work.std_arith.all;
ENTITY calc is
    Port (Num1: in Signed (1 downto 0);
        Num2: in Signed (1 downto 0);
        S:  in STD_LOGIC_VECTOR (1 downto 0);
        a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;
 
Architecture tris of calc is
signal SUM:Signed (3 downto 0);
signal RES:Signed (3 downto 0);
signal MUL:Signed (3 downto 0);
signal COM:STD_LOGIC_VECTOR (3 downto 0);
begin 
process(Num1,Num2,S)
    BEGIN
    CASE S IS
        WHEN "00"=>SUM<=resize(Num1,4)+Num2; 
        WHEN "01"=>RES<=resize(Num1,4)-Num2;
        WHEN "10"=>
        if Num1>Num2 then 
        COM <= "1110";
        elsif Num1<Num2 then
        COM <= "1011";
        else
        COM <= "1010";
    end if;
        WHEN OTHERS=>MUL<=(Num1*Num2);
        END CASE;
        END PROCESS;  
process (SUM)
    begin
        case SUM is
            when "0000"=> a_to_g <="0000001";  --0
            when "0001"=> a_to_g <="1001111";  --1
            when "0010"=> a_to_g <="0010010";  --2
            when "0011"=> a_to_g <="0000110";  --3
            when "0100"=> a_to_g <="1001100";  --4
            when "0101"=> a_to_g <="0100100";  --5
            when "0110"=> a_to_g <="0100000";  --6
            when "0111"=> a_to_g <="0001101";  --7
            when "1000"=> a_to_g <="0000000";  --8
            when "1001"=> a_to_g <="0000100";  --9
end case;
    end process;
process (RES)
    begin
        case RES is
            when "0000"=> a_to_g <="0000001";  --0
            when "0001"=> a_to_g <="1001111";  --1
            when "0010"=> a_to_g <="0010010";  --2
            when "0011"=> a_to_g <="0000110";  --3
            when "0100"=> a_to_g <="1001100";  --4
            when "0101"=> a_to_g <="0100100";  --5
            when "0110"=> a_to_g <="0100000";  --6
            when "0111"=> a_to_g <="0001101";  --7
            when "1000"=> a_to_g <="0000000";  --8
            when "1001"=> a_to_g <="0000100";  --9
end case;
    end process;
process (MUL)
    begin
        case MUL is
            when "0000"=> a_to_g <="0000001";  --0
            when "0001"=> a_to_g <="1001111";  --1
            when "0010"=> a_to_g <="0010010";  --2
            when "0011"=> a_to_g <="0000110";  --3
            when "0100"=> a_to_g <="1001100";  --4
            when "0101"=> a_to_g <="0100100";  --5
            when "0110"=> a_to_g <="0100000";  --6
            when "0111"=> a_to_g <="0001101";  --7
            when "1000"=> a_to_g <="0000000";  --8
            when "1001"=> a_to_g <="0000100";  --9
end case;
    end process;
process (COM)
    begin
        case COM is
            when "1010"=> a_to_g <="1000001";  --=
            when "1011"=> a_to_g <="1001110";  --<
            when "1110"=> a_to_g <="1111000";  -->
            when others => a_to_g <="0000000";
        end case;
    end process;
end tris;
 
Last edited by a moderator:

but my case ended with: when others multiply
 

There may be more errors, but every case construct must have an others alternative (it might be empty).

- - - Updated - - -

I was talking about every case construct, not only some of it.

There are indeed more errors:
- inconsistent library use statements

What is work.std_arith? Do you mean ieee.std_logic_arith? You should remove the non-standard numeric libraries and preserve numeric_std only.

- multiple drivers error

The processes are writing to the same signal a_to_g which is not possible.
 
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you are right, it was that library.
so if the processes are writing to the same signal how can I send the answer to the display?
 
Last edited:

Your design misses a selection for the output assignment according to selected calculation mode. Either a multiplexer or an overall case construct with all assignments in a single process.
 
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i just added an if and a signal for the output it says that sum,res,com,mul should be referenced in the sensitivity list. what does it means?
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
ENTITY calc is
	Port (Num1: in Signed (1 downto 0);
		Num2: in Signed (1 downto 0);
		S:  in STD_LOGIC_VECTOR (1 downto 0);
		a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;

Architecture tris of calc is
signal SUM:Signed (3 downto 0);
signal RES:Signed (3 downto 0);
signal MUL:Signed (3 downto 0);
signal COM:Signed (3 downto 0);
signal a_to_g1:signed (3 downto 0);
begin 
process(Num1,Num2,S)
	BEGIN
	CASE S IS
		WHEN "00"=>SUM<=resize(Num1,4)+Num2; 
		WHEN "01"=>RES<=resize(Num1,4)-Num2;
		WHEN "10"=>
		if Num1>Num2 then 
		COM <= "1110";
		elsif Num1<Num2 then
		COM <= "1011";
		else
		COM <= "1010";
	end if;
		WHEN OTHERS=>MUL<=(Num1*Num2);
		END CASE;

  if (S="00") then
  a_to_g1<=SUM;
  ELSIF (S="01") THEN
  a_to_g1<=RES;
    ELSIF (S="10") THEN
  a_to_g1<=COM;
  ELSE a_to_g1<=MUL;
  end if;
  		END PROCESS;
process (a_to_g1)
	begin
		case a_to_g1 is
			when "0000"=> a_to_g <="0000001";  --0
			when "0001"=> a_to_g <="1001111";  --1
			when "0010"=> a_to_g <="0010010";  --2
			when "0011"=> a_to_g <="0000110";  --3
			when "0100"=> a_to_g <="1001100";  --4
			when "0101"=> a_to_g <="0100100";  --5
			when "0110"=> a_to_g <="0100000";  --6
			when "0111"=> a_to_g <="0001101";  --7
			when "1000"=> a_to_g <="0000000";  --8
			when "1001"=> a_to_g <="0000100";  --9
			when "1010"=> a_to_g <="1000001";  --=
			when "1011"=> a_to_g <="1001110";  --<
			when "1110"=> a_to_g <="1111000";  -->
			when others => a_to_g <="0000000";
		end case;
	end process;
end tris;
 

Note the assignments to a_to_g are almost all the same as they are generating the digits. There is another set that produces some symbols.

You should have a single process that drives the display. i.e. one process that drives a_to_g with a 5-bit select. The extra bit is for the COM outputs.

Code: 
signal DISP : std_logic_vector(4 downto 0);
case DISP is
  -- output numbers
  when "00000"=> a_to_g <="0000001";  --0
  when "00001"=> a_to_g <="1001111";  --1
  when "00010"=> a_to_g <="0010010";  --2
  when "00011"=> a_to_g <="0000110";  --3
  when "00100"=> a_to_g <="1001100";  --4
  when "00101"=> a_to_g <="0100100";  --5
  when "00110"=> a_to_g <="0100000";  --6
  when "00111"=> a_to_g <="0001101";  --7
  when "01000"=> a_to_g <="0000000";  --8
  when "01001"=> a_to_g <="0000100";  --9
  -- output symbols
  when "11010"=> a_to_g <="1000001";  --=
  when "11011"=> a_to_g <="1001110";  --<
  when "11110"=> a_to_g <="1111000";  -->
  when others => a_to_g <="0000000";
end case;

The key is now you drive the DISP with the result of the operation and the = > < symbols. That would also be done in a case statement.

- - - Updated - - -

YAI said:
i just added an if and a signal for the output it says that sum,res,com,mul should be referenced in the sensitivity list. what does it means?
Click to expand...
If a signal is read inside a process it needs to be in the sensitivity list. i.e. signals on the right hand side of an assignment and when signals are used in comparisons.
 

so do i have to erase this? besides adding your code?
Code: 
if (S="00") then
  a_to_g1<=SUM;
  ELSIF (S="01") THEN
  a_to_g1<=RES;
    ELSIF (S="10") THEN
  a_to_g1<=COM;
  ELSE a_to_g1<=MUL;
  end if;
  		END PROCESS;
 

The code in #6 was incorrect and doesn't drive the COM LED outputs. You should draw out what you are implementing. Unless you know what the hardware should look like coding on-the-fly ends up resulting in code changes like you are making (somewhat random attempts to get something working).

My suggestion was based on the architecture I would implement for the design, i.e. a display driver (the code in #7), and the logic to generate the DISP signal (i.e. the output of the math operation or the COM output). The code for the later is more like the code you have in the first process (i.e. process (Num1,Num2,S)) in post #6, but all of the selections end up outputting to the same DISP signal. Also making others the multiply was the wrong thing to do...the default case statement is better off assigning X values to the output so you know in the simulation the design is going off into the weeds with S values that don't make sense like S = "xx" or S = "x1" etc. Synthesis will just treat the default clause as a don't care and will optimize the rest of the valid selections. If you have some possible inputs for S that aren't used make sure you do define those if they require that the outputs be a certain value. (this is probably too confusing :-()
 
Last edited:

ok i did as i understood , i think i understand it, but i got some errors after this
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
ENTITY calc is
	Port (Num1: in Signed (1 downto 0);
		Num2: in Signed (1 downto 0);
		S:  in STD_LOGIC_VECTOR (1 downto 0);
		a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;

Architecture tris of calc is
signal SUM:Signed (3 downto 0);
signal RES:Signed (3 downto 0);
signal MUL:Signed (3 downto 0);
signal COM:Signed (3 downto 0);
signal DISP : signed(4 downto 0);
begin 
process(Num1,Num2,S)
	BEGIN
	CASE S IS
		WHEN "00"=>SUM<=resize(Num1,4)+Num2; 
		WHEN "01"=>RES<=resize(Num1,4)-Num2;
		WHEN "10"=>
		if Num1>Num2 then 
		COM <= "1110";
		elsif Num1<Num2 then
		COM <= "1011";
		else
		COM <= "1010";
	end if;
		WHEN OTHERS=>MUL<=(Num1*Num2);
		END CASE;
END PROCESS;
process(Num1,Num2,S)
	BEGIN
	CASE S IS
		WHEN "00"=>SUM<=DISP; 
		WHEN "01"=>RES<=DISP;
		WHEN "10"=>COM<=DISP;
		WHEN others=>MUL<=DISP;
	END CASE;
		END PROCESS;
	
  		
process (DISP)
	begin
		case DISP is
  -- output numbers
  when "00000"=> a_to_g <="0000001";  --0
  when "00001"=> a_to_g <="1001111";  --1
  when "00010"=> a_to_g <="0010010";  --2
  when "00011"=> a_to_g <="0000110";  --3
  when "00100"=> a_to_g <="1001100";  --4
  when "00101"=> a_to_g <="0100100";  --5
  when "00110"=> a_to_g <="0100000";  --6
  when "00111"=> a_to_g <="0001101";  --7
  when "01000"=> a_to_g <="0000000";  --8
  when "01001"=> a_to_g <="0000100";  --9
  -- output symbols
  when "11010"=> a_to_g <="1000001";  --=
  when "11011"=> a_to_g <="1001110";  --<
  when "11110"=> a_to_g <="1111000";  -->
  when others => a_to_g <="0000000";
end case;
	end process;
end tris;
 

You're still just typing away without having a clear vision of HOW the design has to work.

output mux: used to select the character to display. (DISP case statement)
operation mux: used to select the operation (or COM selection) who's result is used to drive DISP. This is one mulitplexer that selects the output an operation.

You currently have the SUM, RES etc driven from two places.
Code VHDL - [expand]
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WHEN "00"=> -- when S is "00" then do...
   -- the following assignment:
     SUM<=resize(Num1,4)+Num2;
WHEN "00"=> -- when S is "00" then do...
   -- the following assignment:
     SUM<=DISP;

You can't do both of these. I could tell you what to write, but that won't help you learn how to think in terms of hardware and what your code represents. Instead of thinking of VHDL as a programming language:
new in .... programing in vhdl
Click to expand...
 
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you were right i wasnt noticing how it work besides that i just started with programing(its my first week) so sorry if i dont get it too quickly,thank you for that, after correcting some mistakes, after that i have this
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
ENTITY calc is
	Port (Num1: in Signed (1 downto 0);
		Num2: in Signed (1 downto 0);
		S:  in STD_LOGIC_VECTOR (1 downto 0);
		a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;

Architecture tris of calc is
signal SUM:Signed (4 downto 0);
signal RES:Signed (4 downto 0);
signal MUL:Signed (4 downto 0);
signal COM:Signed (4 downto 0);
signal DISP: signed(4 downto 0);
begin 
process(Num1,Num2,S)
	BEGIN
	CASE S IS
		WHEN "00"=>SUM<=resize(Num1,5)+Num2;
 		SUM<=DISP;
		WHEN "01"=>RES<=resize(Num1,5)-Num2;
		RES<=DISP;
		WHEN "10"=>
		if Num1>Num2 then 
		COM <= "11110";
		elsif Num1<Num2 then
		COM <= "11011";
		else
		COM <= "11010";
	end if;
		WHEN OTHERS=>MUL<=resize(Num1,3)*Num2;
		MUL<=DISP;
		END CASE;

		END PROCESS;
	
  		
process (DISP)
	begin
		case DISP is
  -- output numbers
  when"00000"=> a_to_g <="0000001";  --0
  when "00001"=> a_to_g <="1001111";  --1
  when "00010"=> a_to_g <="0010010";  --2
  when "00011"=> a_to_g <="0000110";  --3
  when "00100"=> a_to_g <="1001100";  --4
  when "00101"=> a_to_g <="0100100";  --5
  when "00110"=> a_to_g <="0100000";  --6
  when "00111"=> a_to_g <="0001101";  --7
  when "01000"=> a_to_g <="0000000";  --8
  when "01001"=> a_to_g <="0000100";  --9
  -- output symbols
  when "11010"=> a_to_g <="1000001";  --=
  when "11011"=> a_to_g <="1001110";  --<
  when "11110"=> a_to_g <="1111000";  -->
  when others => a_to_g <="0000000";
end case;
	end process;
end tris;
 

DISP is supposed to be on the Left Hand Side (LHS) of the assignments. You have it on the RHS, which means it never gets assigned anything. You should run the code on a simulator, you would have seen the DISP staying X throughout the simulation.

And what do you expect to happen here?
Code: 
CASE S IS
  WHEN "00"=>
      SUM<=resize(Num1,5)+Num2;
      SUM<=DISP;
You assign SUM then reassign it with DISP, so instead of doing a sum you end up with SUM being an X.

Once again VHDL isn't programming, it's a description language (i.e. writing hardware circuits (RTL) instead of drawing hardware circuits (Schematics)).
 
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i was expecting to take the result as the exit of the display.
ok my description of the its like this:
when s="00" do the sum and show the result in the display.

with that i assume that first i have to put a case for the operation and later a case for the display this case must say when s=00 then disp=sum

- - - Updated - - -

i only have 1 error it says that logic equation has too many product terms on sinal a_to_g(3):

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
ENTITY calc is
    Port (Num1: in Signed (1 downto 0);
        Num2: in Signed (1 downto 0);
        S:  in STD_LOGIC_VECTOR (1 downto 0);
        a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;
 
Architecture tris of calc is
signal SUM:Signed (4 downto 0);
signal RES:Signed (4 downto 0);
signal MUL:Signed (4 downto 0);
signal COM:Signed (4 downto 0);
signal DISP : signed(4 downto 0);
begin 
process(Num1,Num2,S)
    BEGIN
    CASE S IS
        WHEN "00"=>SUM<=resize(Num1,5)+Num2;
        WHEN "01"=>RES<=resize(Num1,5)-Num2;
        WHEN "10"=>
        if Num1>Num2 then 
        COM <= "11110";
        elsif Num1<Num2 then
        COM <= "11011";
        else
        COM <= "11010";
    end if;
        WHEN OTHERS=>MUL<=resize(Num1,3)*Num2;
        END CASE;
END PROCESS;
PROCESS (S,SUM,RES,MUL,COM)
BEGIN
IF (S="00") THEN DISP<=SUM;
ELSIF (S="01") THEN DISP<=RES;
ELSIF (S="10") THEN DISP<=COM;
ELSE DISP<=MUL;
    END IF;
        END PROCESS;    
        
process (DISP)
    begin
        case DISP is
  -- output numbers
  when "00000"=> a_to_g <="0000001";  --0
  when "00001"=> a_to_g <="1001111";  --1
  when "00010"=> a_to_g <="0010010";  --2
  when "00011"=> a_to_g <="0000110";  --3
  when "00100"=> a_to_g <="1001100";  --4
  when "00101"=> a_to_g <="0100100";  --5
  when "00110"=> a_to_g <="0100000";  --6
  when "00111"=> a_to_g <="0001101";  --7
  when "01000"=> a_to_g <="0000000";  --8
  when "01001"=> a_to_g <="0000100";  --9
  -- output symbols
  when "11010"=> a_to_g <="1000001";  --=
  when "11011"=> a_to_g <="1001110";  --<
  when "11110"=> a_to_g <="1111000";  -->
  when others => a_to_g <="0000000";
end case;
    end process;
end tris;
 
Last edited by a moderator:

i need help please this vhdl its for tomorrow!!

i need to do a calculator of 2 bits which can add,subtract,multiply and compare between the numbers, i think that im close to the end, now it says that logic equation has too many product terms on signal a_to_g(3).please help its for tomorrow!!! and all must be displayed in a 7 segment display.
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.numeric_std.ALL;
ENTITY calc is
	Port (Num1: in Signed (1 downto 0);
		Num2: in Signed (1 downto 0);
		S:  in STD_LOGIC_VECTOR (1 downto 0);
		a_to_g:out STD_LOGIC_VECTOR (6 downto 0));
end calc;

Architecture tris of calc is
signal SUM:Signed (4 downto 0);
signal RES:Signed (4 downto 0);
signal MUL:Signed (4 downto 0);
signal COM:Signed (4 downto 0);
signal DISP : signed(4 downto 0);
begin 
process(Num1,Num2,S)
	BEGIN
	CASE S IS
		WHEN "00"=>SUM<=resize(Num1,5)+Num2;
 		WHEN "01"=>RES<=resize(Num1,5)-Num2;
		WHEN "10"=>
		if Num1>Num2 then 
		COM <= "11110";
		elsif Num1<Num2 then
		COM <= "11011";
		else
		COM <= "11010";
	end if;
		WHEN OTHERS=>MUL<=resize(Num1,3)*Num2;
		END CASE;
END PROCESS;
PROCESS (S,SUM,RES,MUL,COM)
BEGIN
IF (S="00") THEN DISP<=SUM;
ELSIF (S="01") THEN DISP<=RES;
ELSIF (S="10") THEN DISP<=COM;
ELSE DISP<=MUL;
	END IF;
		END PROCESS;	
  		
process (DISP)
	begin
		case DISP is
  -- output numbers
  when "00000"=> a_to_g <="0000001";  --0
  when "00001"=> a_to_g <="1001111";  --1
  when "00010"=> a_to_g <="0010010";  --2
  when "00011"=> a_to_g <="0000110";  --3
  when "00100"=> a_to_g <="1001100";  --4
  when "00101"=> a_to_g <="0100100";  --5
  when "00110"=> a_to_g <="0100000";  --6
  when "00111"=> a_to_g <="0001101";  --7
  when "01000"=> a_to_g <="0000000";  --8
  when "01001"=> a_to_g <="0000100";  --9
  -- output symbols
  when "11010"=> a_to_g <="1000001";  --=
  when "11011"=> a_to_g <="1001110";  --<
  when "11110"=> a_to_g <="1111000";  -->
  when others => a_to_g <="0000000";
end case;
	end process;
end tris;
 

FvM said:
There may be more errors, but every case construct must have an others alternative (it might be empty).
Click to expand...
To be strict, the requirement is that all possible combinations are covered. This is difficult without "others" for std_logic based types which can have 'X', 'H', 'Z' etc. For some types it is possible to list all cases, and "others" can then be removed. If you want to handle all possible cases explicitly it is an advantage to remove "others", because the compiler will then give an error if any case is missing.
 

well it says like this: Error: Logic equation has too many product terms on signal a_to_g(3).

i think its the part of the comparator, cause i dont know exactly how to tell him how it should manage the 3 comparations in one statement.
when i erased everything related with the comparator it says this:

Error: Signal sum_4 can not be placed on device.
Error: Signal sum_2 can not be placed on device.
Error: Signal res_4 can not be placed on device.
Error: Signal res_2 can not be placed on device.
Error: Signal sum_3 can not be placed on device.
Error: Signal res_3 can not be placed on device.
Error: Signal mul_2 can not be placed on device.
Error: Signal mul_1 can not be placed on device.
Error: Signal \MODULE_3:g1:a0:g1:u0:cl(0):cm(2):c4:bs\ can not be placed on device.
Error: Signal sum_0 can not be placed on device.
Error: Signal res_0 can not be placed on device.
Error: Signal \MODULE_3:g1:a0:g1:u0:cl(0):cm(1):c1:bs\ can not be placed on device.
Error: Signal \MODULE_3:g1:a0:g1:u0:sg:u0\ can not be placed on device.
Error: Signal \MODULE_2:g1:a0:g0:u0:gs:g1:us0\ can not be placed on device.
Error: Signal \MODULE_1:g1:a0:g0:u0:ga:g1:ua0\ can not be placed on device.
Error: Signal \MODULE_1:g1:a0:g0:u0:ga:t1:ga0(1):u3\ can not be placed on device.
Error: Signal \MODULE_2:g1:a0:g0:u0:gs:t1:gs0(1):u3\ can not be placed on device.
Error: Signal mul_4 can not be placed on device.
Error: Signal mul_3 can not be placed on device.
Error: Signal mul_0 can not be placed on device.
Error: Signal \MODULE_3:g1:a0:g1:u0:cl(1):cm(1):c1:bs\ can not be placed on device.
Error: Signal \MODULE_3:g1:a0:g1:u0:cl(0):cm(1):c1:bc\ can not be placed on device.
Error: Signal \MODULE_2:g1:a0:g0:u0:gs:t1:gs0(1):gss:u2\ can not be placed on device.
Error: Signal \MODULE_2:g1:a0:g0:u0:gs:t1:gs0(1):gss:u1\ can not be placed on device.
Error: Signal \MODULE_1:g1:a0:g0:u0:ga:t1:ga0(1):gas:u2\ can not be placed on device.
Error: Signal \MODULE_1:g1:a0:g0:u0:ga:t1:ga0(1):gas:u1\ can not be placed on device.

why it says this?its for a GAL 22V10D-25PC
 

why it says this?its for a GAL 22V10D-25PC
Click to expand...
10 macro cells is simply too small. I compiled the post #15 design for MAX3000A, which has roughly a similar CPLD macro cell topology and it needs 54 macro cells.

I believe that the design can be reduced. Presently the compiler is indicating inferred latches which shouldn't happen for purely combinational logic. Less than 32 macro cells sounds unlikely, though.
 

so its there any way i can make it fit it on a gal? how? Besides that does it gave you an error or somethig like that when you compile it?
 

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