thverda
Newbie level 1
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:58:05 02/15/2013
-- Design Name:
-- Module Name: sevencounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SECONDCOUNTER is
Port ( nRST : in STD_LOGIC;
CLK : in STD_LOGIC;
LED : out STD_LOGIC
);
end SECONDCOUNTER;
architecture Behavioral of SECONDCOUNTER is
signal sec_cnt : unsigned(25 downto 0);
signal min_cnt : unsigned ( 8 downto 0);
begin
-- it is for counting one second.
process(CLK, nRST)
begin
if nRST = '0' then
sec_cnt <= (others => '0');
elsif rising_edge(CLK) then
if sec_cnt = ("11" & X"000000") then
sec_cnt <= (others => '0');
else
sec_cnt <= sec_cnt + 1;
end if;
end if;
end process;
----------------------------------
-- LED every one second, LED will turn on , turn off...
process(CLK, nRST)
begin
if nRST = '0' then
LED <= '1';
elsif rising_edge(CLK) then
if sec_cnt = ("01" & X"800000") then
LED <= '1';
elsif sec_cnt = ("11" & X"000000") then
LED <= '0';
end if;
end if;
end process;
----------------- it is for counting min.
process( CLK, nRST)
begin
if nRST = '0' then
LED <= '1';
elsif rising_edge(CLK) then
if sec_cnt = ("11" & X"000000") then
min_cnt<=min_cnt+1;
end if;
end if;
case min_cnt is
when "000111100" => LED<='1';
when "001111000" => LED<='0';
when "010110100" => LED<='1';
when "011110000" => LED<='0';
when "100101100" => LED<='1';
when "101101000" => LED<='0';
when others => min_cnt<=min_cnt;
end case;
end process;
end Behavioral;
-------------------------------------------------
i will use seven segment . i used case . now LED used in the case. later i will use sevensegment instead of LED. LED is just for test.
anyway....
it does not work..
erro messeage is that
WARNING:Xst:819 - "D:/LIMJIYOUNG/vhdl/sevencounter_0215/sevencounter.vhd" line 80: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<min_cnt>
ERROR:Xst:827 - "D:/LIMJIYOUNG/vhdl/sevencounter_0215/sevencounter.vhd" line 80: Signal min_cnt cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
what is the problem?????
-- Company:
-- Engineer:
--
-- Create Date: 10:58:05 02/15/2013
-- Design Name:
-- Module Name: sevencounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SECONDCOUNTER is
Port ( nRST : in STD_LOGIC;
CLK : in STD_LOGIC;
LED : out STD_LOGIC
);
end SECONDCOUNTER;
architecture Behavioral of SECONDCOUNTER is
signal sec_cnt : unsigned(25 downto 0);
signal min_cnt : unsigned ( 8 downto 0);
begin
-- it is for counting one second.
process(CLK, nRST)
begin
if nRST = '0' then
sec_cnt <= (others => '0');
elsif rising_edge(CLK) then
if sec_cnt = ("11" & X"000000") then
sec_cnt <= (others => '0');
else
sec_cnt <= sec_cnt + 1;
end if;
end if;
end process;
----------------------------------
-- LED every one second, LED will turn on , turn off...
process(CLK, nRST)
begin
if nRST = '0' then
LED <= '1';
elsif rising_edge(CLK) then
if sec_cnt = ("01" & X"800000") then
LED <= '1';
elsif sec_cnt = ("11" & X"000000") then
LED <= '0';
end if;
end if;
end process;
----------------- it is for counting min.
process( CLK, nRST)
begin
if nRST = '0' then
LED <= '1';
elsif rising_edge(CLK) then
if sec_cnt = ("11" & X"000000") then
min_cnt<=min_cnt+1;
end if;
end if;
case min_cnt is
when "000111100" => LED<='1';
when "001111000" => LED<='0';
when "010110100" => LED<='1';
when "011110000" => LED<='0';
when "100101100" => LED<='1';
when "101101000" => LED<='0';
when others => min_cnt<=min_cnt;
end case;
end process;
end Behavioral;
-------------------------------------------------
i will use seven segment . i used case . now LED used in the case. later i will use sevensegment instead of LED. LED is just for test.
anyway....
it does not work..
erro messeage is that
WARNING:Xst:819 - "D:/LIMJIYOUNG/vhdl/sevencounter_0215/sevencounter.vhd" line 80: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<min_cnt>
ERROR:Xst:827 - "D:/LIMJIYOUNG/vhdl/sevencounter_0215/sevencounter.vhd" line 80: Signal min_cnt cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
what is the problem?????
