I need help with subthreshold design

[ranair123]

Help Subthreshold Design

I am having some problem in making the transistors operate in weak inversion. The circuit attached is used as a sum-product block.
All the input currents can range between 0 to 1 uA.

Iy0 + Iy1 <= 1uA
Ix0 + Ix1 <= 1uA

The NMOS transistors M1 to M10 have the dimensions [W=5um, L=0.5um].

I am using,
Vbx to make M3, M5 operate in weak inversion region and
Vby to make M1, M2 operate in weak inversion region.

No matter what value i set Vbx and Vby, the Vgs for these transistors are not changing.

According to my understanding, to make these transistors operate in weak inversion the gate to source voltage should be below 200mV (to get the current proportional to exponent of Vgs)

Can anyone tell me whether the method I am using to setup this is correct or wrong. And is my understanding correct?

Thanks,
ranair123

PS: NMOS M11 [w=4um L=4um] is operating in as a current source of 1uA.

 

[|IAngel|]

Re: Help Subthreshold Design

I don't have time to look tonight, but to get the FETs in subthreshold, all you need is to ensure that VGS<VT. That puts you in "cutoff" (now named subthreshold, as it can still be used for making active devices).

No process (short of Low VT devices) has a VT that low. For sub-threshold use, you should have Vgs < 400mV. The lower in the region, the more linear and less likely it will drift into medium-inversion, but the slower it will be.

I can look at this tomorrow if no one else has covered it.

 

[pthoppay]

Re: Help Subthreshold Design

Hi,

What are the dimensions which you have kept for M3 and M5? As said earlier it is hard to make a transistor work in weak inversion from Vgs point of view. But since here current is fixed, what you could do is increase the size of transistor and there by push the transistor from strong inversion to weak inversion for a given current.

In my opinion it is the best method to do.

If you want these things from mathematical point of view let me know.

Regards,
Prakash.

 

[ranair123]

Re: Help Subthreshold Design

@ Prakash,

The transistors are of dimensions [W=5um, L=0.5um].
I want to know if sizing of the transistors was a solution, then I can as well remove the reference voltages Vbx and Vby isnt it?

@ |IAngel|

The threshold voltage of transistors I am using is in the 0.65 V. And all the transistors are operating with Vgs less than 0.65 V, which I think is the so called subthreshold region.

But here the current is not exactly proportional to the exponent of Vgs. what i did was, I plotted d(ln(Id))/d(Vgs) and only for Vgs < 0.2 V, the plot was constant. So i thought only in this region it is exponential.


My other confusion is,
Shouldnt the reference voltages Vbx and Vby have any effect on the Vgs??? or in this particular circuit, they are used to make the MOS 7,8,9,10 operate below threshold?

Kindly pardon my ignorance confusion about the concepts itself.

 

[pthoppay]

Re: Help Subthreshold Design

Hi,

I didnt analyse your circuit fully. But when I glanced through it, to operate M1.M2,M3,M5 in W.I, what I would do is the following.

1) As you said, the biasing is not necessary if you scale your transistor, but beware your transistor are going to be big enough.
2)Remove the biasing, and ground the source of all NMOS.
3)Given the amount of current each transistors are carrying

Ex M1,M5 0.7 u
M2, M3 0.3u

First calculate Ilim=2*μ*W/L*Cox*n*Ut^2 (you dont know W/L, leave it as variable)

Where n=1+(cd/cox), could assume around 1.5 for nmos.

Then to operate transistors in W.I have Ilim = I*8 , calculate W/L from this.

Fix W/L and you will see the transistors operating in W.I. (For ex. I=0.7 u*8= 5.6u is Ilim calculate W/L from this).

Let me know if you face any probelms.


For your another question of, current vs Vgs not being linear can be due to the dependence on "n" at higher voltages, where "n" has the meaning as defined above. Actually Id is protional to exp(Vgs/nVt) and not exp(Vgs/Vt) during sub-threshold regime.
Regards,
Prakash.

 

[pseudockb]

Re: Help Subthreshold Design

I think Prakash has made a point in how to bias the xtors in weak inversion. I would suggest also try to plot a curve of ln(Id) vs Vgs. The linear region of the curve is where you got your weak inversion region.