I need help VHDL 16 bit Parallel adder.

Status
Not open for further replies.
W

wjswkvk208

Newbie level 1
Joined
May 8, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
6
I made fullAdder.

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
	port(a, b, z : in  std_logic;
		 s, c : out std_logic);

end fulladder;

architecture dataflow of fulladder is
signal t1, t2, t3 : std_logic;
begin
	t1 <= a XOR b;
	t2 <= a AND b;
	s <= t1 XOR z;
	t3 <= t1 XOR z;
	c <= t2 OR t3;
end dataflow;

How to make 16 bit Parallel adder? plz get me a code..
 

In vhdl, an adder is "+", two input vector of 16bits added together provides a 17bits output, you need to add saturation behind, that's it.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…