[SOLVED] i need help making a 24 h adjustable digital clock with 74192 and 7447 and 7 segment on Proteus

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shirotpoison

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so i have 2 counters for seconds an 2 counters for munits the problem is how to connect the second block with the munits block ,when i add a AND gate it glitched the munits counter hits 1 on 40 second , i add an RC circuit it make seconds reech 60 but the munits steel go 1 on 40 seconds , So any solution of how to connects the two blocks together correctly
 

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When I've tried to coordinate two or more counters (or logic gates) there have been situations where it mattered whether a change of state occurs in a downward direction or an upward direction, in order to create some desired behavior.

Sometimes it requires putting an invert-gate somewhere (maybe before a device, or after a device).

And related parameter... How to distinguish whether a device is or should be built so it is:
a) level-triggered,
b) positive-edge-triggered,
c) negative-edge-triggered?

I can't predict what trick will work. The first thing I try seldom is the answer. So then I start trying different things, maybe even randomly. If I'm lucky I'll get some insight into the answer to what's needed to coordinate digital events and finally make progress.
 

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Wow. Designing with “tricks”, “luck”, and “random” things???

How about using timing analysis, knowledge, simulation?
 

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hit me up if you find somthing
 

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My suspicion is that the outputs of the 74192 are not entirely 'clean' due to propagation delays within the chip. If the outputs are 0x0011 (i.e. decimal 3) and the chip increments, the 3rd bit may go high (i.e. have an output of 0b0111) for a fraction of a second before the lower bits go low to give 0x0100. If that is the case then the AND gate will see the 'glitch' and set its output - also for a fraction of a second but enough for the subsequent circuitry to respond and reset on the '4' (or 40 seconds as mentioned in Post #1).
My suggestion earlier was to use a divide-by-6 chip which is the 7492. (Actually it is a divide-by-12 but you use the Qd output as the trigger to reset and increment the next higher digit circuit.)
Susan
 

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am onley allow to use 74192
 

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The 74LS172 is a synchronous counter, not an asychronous counter. All 4 of the Q outputs should change at the same time. I put together
the 4 counters and AND gates from circuit shown, less the resistors, capacitors, 74LS47 decoders and 7 segment displays, on a breadboard and it works fine using individual LED's to display the count. A breadboard is generally a noisy environment, but it's not showing any glitches. In the description header for the post, you mention this project is being done on Proteus. Has an actual clock been made or is this just a simulation ? The 74LS192 is a synchronous chip, but is Proteus having trouble simulating it as such ?
 

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Even a synchronous counter will have skew between outputs. Further, propagation times are different between rising and falling edges. NOTHING changes at exactly the same time, even synchronous circuits.
 

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This may or may not create glitches...
Your schematic shows dissimilar connections for pins 4, 11 among the 74192's.
On two IC's the pins are connected together and pulled high being unused. This appears correct.
The other two 74192 have those pins connected together but to nothing else.

Pin 4 is count down. 11 is Load. Advice tells us 'all inputs should be connected to something. Leave no input floating.'
 

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