I need help for Synopsys Tetramax

[dhaval4987]

I have a netlist for which I wish to generate test patterns.

My doubt is: for running drc, this tools asks for SPF file. I know it is possible to generate SPF file. but to generate it, this tool needs scan chain information. I have completely no idea where to get that?

Any help regarding how to get scan chain info? Or how to generate SPF? My deisgn is a simple combinational design and i wish to generate patterns for path delay. Is it possible to generate without having any of this information?

Thanks!

 

[honey13]

Hi dhaval,

We get the SPF file during scan insertion stage.Use synopsis dc for inserting the scan.

From the spec you can get the information about the max lenght of the scan chain, number of scan_chains, number of scan clocks, their frequencies, clock_controller block (in case if there is) .

Provide these information to the tool during scan insertion and write out the .spf file.

We cannot generate the patterns without having all the above info.

 

[dhaval4987]

Oh..

from which specs do i get the information about scan chain, scan clocks, friequencies, etc?

I checked dc tutorial, could not find how to insert scan. all i found was how to disable reporting of scan chain violation and in one section i found out how to replace all sequential elements with scan elements to optimize the design- which in my case is none coz i have fully combinational design.

also i read about synopsys dft compiler which is used for test synthesis. not sure if i will have to learn and use that or not.

Let me know...

 

[avinashch]

you only need spf only if you have scan chains inserted in your design. if you don't have that in your design you can skip this step and generate the test patterns.

 

[dhaval4987]

Ok. Thank you Avinash. Have you ever done this? I got more confused with Scan Elements because I want to use Path Delay model for delay calculation- which only works in combinational design. If I introduce scan elements in design- that makes my design combinational (I guess!??) and so I cant use Path delay model.

Have you ever used without spf? Does it generate patterns without performing drc? Is there any general flow chart? I have never used tetramax!

 

[avinashch]

Sorry to reply late. I have done this. The thing is scan chain is always performed in sequential circuits. You dont have scan chains in a combinational logic so whenever you introduce a scan chain it changes the design to sequential.

 

[dhaval4987]

Ok. One more question.

While generating a patterns, does it always take just one path only or it takes the entire circuit?

 

[avinashch]

It considers the entire circuit.

 

[dhaval4987]

But like its mentioned here, in the flowchart for path delay model- it says we need to feed in the critical paths!

I am confused.

Also- I did the way you suggested:

First I read verilog library along with verilog netlist of circuit, and then run the DRC- it shows no error.

But in ATPG stage- when I try to run the model with path delay model- it shows no faults detected/covered and generates no patterns...

Can you help me figuring out a perfect flow? Where am I going wrong?