I need help about PLL design steps, what should be known???

[ahmad_abdulghany]

Hello all, please pay attention for five minutes, and kindly participate me to think in this issue....

I studied some, not too little, topics concerning PLL and its application in the MS-ASIC desig, ...

starting from understanding basic PLL with PD and its differene types and orders (up to type II third order) ...

then, passed to CP-PLL, studied its basic operation, and itroduced the phase noise issue, and also studied contribution of increasing order and type of different parameters such as speed and phase noise (up to type II third order)

This was mainly for basic PLL..

Also, for PLL applications, I studied how can it be used as FM or FSK modulator/demodulator as well as in case of PSK... also, frequeny synthesizers with PLL either with interger or fractional N ...

Also, studied CDRs; different types of them, and adv/disadvantages of each over the other..

BUT, this was mainly in the block diagrams view, or in other words, in SYSTEM level point of view, with little circuits of different VCO's configurations, PFD's, filters, ...etc. but not in the level of deep circuit design, and hence, no layout, no verification...

NOW, the problem is, I'm supposed to work in a project of PLL design, and i have to en-force or enhance too manythings before i go through that project.. that's i'm looking forward to know from you,

I hope to see your comments

sorry for the long topic..
Thanks alot in advance,
Ahmad,

 

[mooner]

Re: I need help about PLL design steps, what should be known

If on the chip level design , you should have some idea about the different circuits configuration in details, and about simulation method to verify your circuits.

 

[khouly]

Re: I need help about PLL design steps, what should be known

**u should know very well , how to simulate the PLL on system level in all domain time , frequency , and be very good in phase noise analysis of the PLL

**then the circuit level , the charge pump circuit , and earch topology of it , and the range of frequency
VCO , ring , or LC and so on , the high speed dividers , the loop filter design, and how it can be integrated on the chip
the PFD nonidealities , and how to avoid and enhance the performance

many manythings , simualtion tools that will help u in PLL simulation very fast

khouly

 

[ahmad_abdulghany]

Re: I need help about PLL design steps, what should be known

also, floor plan, and layout, back end verification, ... etc..

what i want to know now, can these things been learnt easily or not? and can this be alone, i.e. self study?

what're references should i refer to?

Regards,
Ahmad,

 

[khouly]

Re: I need help about PLL design steps, what should be known

u know all these things can be learnt , but the most important is the practical expeince , this mena that u should do it by ur hand , layout , floor paling and so on , these task need experince

khouly

 

[nickoo]

Charge-pump proccess:
1.select VCO type and design
2.sim the VCO->get KVCO
3.design loopattention BW<<Win)
_a.open loop-->max Phase Margin
_b.close loop-->damping factor and natural freq(min ripple)
4.low-pass filter parameter is decided by step 3.
5.design charge-pump,pay attention the current mismatch
6.desing PFD and divider etc.

 

[shaikhsarfraz]

Re: I need help about PLL design steps, what should be known

Hi,
For designing PLL start with which circuit you will be using phase error detection. Whether an multiplier or PFD with charge pump.

Then select the Loop filter parameters. Then comes the selction of VCO (It can be done earlier also).

For step by step design process go for Notes by Dean Banerjee

thanks
sarfraz

 

[ahmad_abdulghany]

Re: I need help about PLL design steps, what should be known

First, I want to thank you all for your very usefull participation,
and go continue more ..

sarfraz
Thanks for comment, and i want to say that the PLL will be used to satisfy certain wireless standard, may be ZigBee or bluetooth or whtatever, so, how to, first, get that standard parameters, second, to extract required system parameters descrbing the suitable PLL?

also, please upload Notes by Dean Banerjee you mentoned above..

Thanks in advance,
Ahmad,

 

[RFDave]

Re: I need help about PLL design steps, what should be known

Dean Banerjee's Design notes are here

**broken link removed**


Dave
www.keystoneradio.com

 

[shaikhsarfraz]

Re: I need help about PLL design steps, what should be known

Hi,
I think you might have got the Dean Banerjee notes.

Now for desiging PLL for certain specs, you have to be clear with the design process. Then the implementation can be easier. For design flow refer to the notes.

thanks
sarfraz

 

[holddreams]

Re: I need help about PLL design steps, what should be known

Where can i download Dean Banerjee notes ?

 

[adwxl]

Re: I need help about PLL design steps, what should be known

How can I do the systme level simulation?

 

[henryhd]

maybe i also want the simulation

 

[manish12]

Re: I need help about PLL design steps, what should be known

keep the book of Bekar with you.

 

[walkingsun]

Re: I need help about PLL design steps, what should be known

refer to some thesis

 

[Usmanaih]

Re: I need help about PLL design steps, what should be known

Nice:idea:

 

[TILAK_KUMAR]

I am writing the code for PLL in matlab, i would need some of the design steps for VCO and the feed back loop..