I have a Carno table problem

Similar threads

• X

  Still have problem with understanding `include in Verilog

  • Started by Xenon02
  • Oct 2, 2023
  • Replies: 8

  PLD, SPLD, GAL, CPLD, FPGA Design
• R

  problem of fpga

  • Started by rllv24
  • Mar 24, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Which simulator should I use for verilog?

  • Started by electronicslab
  • Oct 26, 2024
  • Replies: 9

  PLD, SPLD, GAL, CPLD, FPGA Design
• Have a timing problem with source synchronous DDR interface

  • Started by ILIA KALISTRU
  • Oct 8, 2022
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Which one should I learn today? Verilog or Systemverilog?

  • Started by electronicslab
  • Oct 27, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design