I have 2 questions regarding spartan II

[Vonn]

1- I know that During the loading of configuration data, a CRC value
embedded in the configuration file is checked against a CRC value
calculated within the FPGA. This is done to make sure that the config.
file has no problem during the loading . Is there any similar technique
to check the data file during the normal operation ? I mean After the
The FPGA is already loaded and It's now working in the system ;
The spartan is SRAM-based , so there is a possibility for the data
file to be corrupted .. hence, it should have a technique to give
indication if this file is corrupted

2- The configuration file of my FPGA is designed to be loaded from a
serial EPROM ,Now the question is How much time exactly it takes for
a SpartanII 200k to be loaded by the configuration file from a serial
EPROM in Master serial mode ? Because the processor should access
the FPGA after it's already starts working in normal operation...
So I have to know this time exactly .

 

[Al Farouk]

Regarding the first question
1- I think the space hardned chips may contain a tequice like that, so advice xilinx for mainly space hardned chips.

2- you can use the done signal to indicate the configuration completion to the u processor.

 

[maestor]

Hi Vonn,

About the 1st question, I know you can enable readback when you generate your bit stream and then via JTAG/Config Pins read the configuration back at any time.

2nd question, to calculate the time you do as always

- size of the file in bits, let's say 314Kbytes = 2,572,288 bits (check the datasheet fpr XC2S parts or your .BIT file or .EXO...)
- when you generate your bitstream there is an option to specify the frequency of the FPGA configuration clock (FPGA is the master so it drives the clock), let's say 5MHz (check it yourself) => 0.5144576 seconds

I wouldn't suggest you to speed up that clock, because is crap, yes crap. If you check it with the scope you'll get Jitter and unaccurate frequencies.

I hope it helps,
-maestor

 

[Aoxomox]

Hi Vonn,

-> 1) **broken link removed**
some usefull information on that

-> 2) on my spartan2e board a DSP boots the FPGA through a SPI port (any other synchronous serial port is ok). In serial master mode the FPGA generates internally a osccillation singal that is crap. But with an external signal the speed can be as high as 50MHz. But for what purpose do you need this high speed if the data may be corrupt???
For booting verification the /Done signal is read back. Additionally the FPGA has in my case an identification string register. if this information can not be read properly then the stored file may be wrong or something else went wrong.
storing the FPGA program in onboard flash memory of the DSP reduces component counts (costs) and increases flexibility.


hope it helps,

aOxOmOx