[SOLVED] i got a problem in the output of the following module. i need help to solve this

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Shyam Joe

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I'm writing a coding for 256 bit adder using 64 bit adders and multiplexer
the coding is as follows
Code: 
module add(a,b,cin,c1,c2,c3,c4,co);
input [255:0] a,b;
input cin;
output [63:0] c1,c2,c3,c4;
output co;
wire [63:0] d,e,f,g,h,i,j,k,l,m,q,r,s,t;
wire n,o,p;
addc a1(q,n,a[63:0],b[63:0],cin);
addcc a2(d,a[127:64],b[127:64]);
addcc a3(e,a[127:64],b[127:64]);
addccc a4(j,o,a[191:128],b[191:128]);
addccc a5(k,p,a[191:128],b[191:128]);
addcc a6(f,a[255:192],b[255:192]);
addcc a7(g,a[255:192],b[255:192]);
addcc a8(h,a[255:192],b[255:192]);
addcc a9(i,a[255:192],b[255:192]);
mux a10(r,d,e,n);
mux a11(l,f,g,o);
mux a12(m,h,i,p);
mux a13(s,j,k,n);
mux a14(t,l,m,n);
assign c1=q;
assign c2=r;
assign c3=s;
assign c4=t;
assign co=n;
endmodule
The sub module codings are as follows
addc:
Code: 
module addc(a,b,cin,s,co);
input [63:0] a,b;
input cin;
output [63:0] s;
output co;
wire [64:0]si;
assign si=a+b+cin;
assign s=si[63:0];
assign co=si[64];
endmodule
addcc:
Code: 
module addcc(a,b,s);
input [63:0] a,b;
output [63:0]s;
assign s=a+b;
endmodule
addccc:
Code: 
module addccc(a,b,s,co);
input [63:0] a,b;
output [63:0] s;
output co;
wire [64:0] si;
assign si=a+b;
assign s=si[63:0];
assign co=si[64];
endmodule
mux:
Code: 
module mux(a,b,s,y);
input [63:0] a,b;
input s;
output [63:0] y;
reg [63:0] y;
always @(s)
case(s)
1'b0: y=a;
1'b1: y=b;
endcase
endmodule
when i simulate dis i get the output as follows
View attachment output.doc
help me to solve it
 

Hi, Shyam joe

What kind of tool are you using?
 

Define Initial values for register y;


in VHDL we write :
signal y:std_logic_vector(63 downto 0):=(others=>'0');
 

Port Map said:
Define Initial values for register y;


in VHDL we write :
signal y:std_logic_vector(63 downto 0):=(others=>'0');
Click to expand...

Actually the problem is in the coding i posted first. there is no such signal y in tat.
 

Shyam Joe,

I've found some serious issues in your original post. For starters:
Code Verilog - [expand]
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module add(a,b,cin,c1,c2,c3,c4,co);
input [255:0] a,b;
input cin;
output [63:0] c1,c2,c3,c4;
output co;
addc a1(q,n,a[63:0],b[63:0],cin);

in the a1 isntance b and cin are defined as inputs in the module ports, but the definition below...
Code Verilog - [expand]
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module addc(a,b,cin,s,co);
input [63:0] a,b;
input cin;
output [63:0] s;
output co;

s and co are outputs, therefore you have an output of a module connected to the input of the top level module. All of your instances suffer from this issue of mis-ordered connections.

you should rewrite the modules using connection by name instantiations and I would switch to C-style module ports from Verilog 2001.
Code Verilog - [expand]
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module add (
  input   [255:0]   a, b,
  input             cin,
  output  [63:0]    c1, c2, c3, c4,
  output            co
);
 
wire [63:0] d,e,f,g,h,i,j,k,l,m,q,r,s,t;
wire n,o,p;
 
// example of what you actually instantiated in
// your code with:
//   addc a1(q,n,a[63:0],b[63:0],cin);
// I'm not sure this is what you intended to do.
addc  a1 (
  .a    (q),
  .b    (n),
  .cin  (a[63:0]),
  .s    (b[63:0]),
  .co   (cin)
);
// I suspect what you wanted connected was this:
addc  a1 (
  .a    (a[63:0]),
  .b    (b[63:0]),
  .cin  (cin),
  .s    (q),
  .co   (n)
);
 
// other instantiations left out for clarity...
 
assign co=n;
 
endmodule


As a side note you should endeavor to use descriptive names for interconnecting wires, reg, etc. Names such as a, b, c, etc don't assist one in understanding what a piece of code is doing. In this case it's a simple adder but anything less than simple will become a maintinence nightmare.

Regards
 

Use named port mapping, or prepare for pain. And as suggested, try descriptive names.
 

ads-eee
thanks for replying. Nw as u said i have modified the code as
Code: 
module add(a,b,cin,c1,c2,c3,c4,co);
input [255:0] a,b;
input cin;
output [63:0] c1,c2,c3,c4;
output co;
wire [63:0] d,e,f,g,h,i,j,k,l,m,q,r,s,t;
wire n,o,p;
addc a1(
  .a    (a[63:0]),
  .b    (b[63:0]),
  .cin  (cin),
  .s    (q),
  .co   (n)
);
addcc a2(
  .a    (a[127:64]),
  .b    (b[127:64]),
  .s    (d)
);
addcc a3(
  .a    (a[127:64]),
  .b    (b[127:64]),
  .s    (e)
);
addccc a4(
  .a    (a[191:128]),
  .b    (b[191:128]),
  .s    (j),
  .co   (o)
);
addccc a5(
  .a    (a[191:128]),
  .b    (b[191:128]),
  .s    (k),
  .co   (p)
);
addcc a6(
  .a    (a[255:192]),
  .b    (b[255:192]),
  .s    (f)
);
addcc a7(
  .a    (a[255:192]),
  .b    (b[255:192]),
  .s    (g)
);
addcc a8(
  .a    (a[255:192]),
  .b    (b[255:192]),
  .s    (h)
);
addcc a9(
  .a    (a[255:192]),
  .b    (b[255:192]),
  .s    (i)
);
mux a10(
  .a    (d),
  .b    (e),
  .s	  (n),
  .y    (r)
);
mux a11(
  .a    (f),
  .b    (g),
  .s	  (o),
  .y    (l)
);
mux a12(
  .a    (h),
  .b    (i),
  .s	  (p),
  .y    (m)
);
mux a13(
  .a    (j),
  .b    (k),
  .s	  (n),
  .y    (s)
);
mux a14(
  .a    (l),
  .b    (m),
  .s	  (n),
  .y    (t)
);
assign c1=q;
assign c2=r;
assign c3=s;
assign c4=t;
assign co=n;
endmodule
and i got the output as attached. Help me to rectify the error
 

Attachments

  • OUTPUT.doc
    153 KB · Views: 59

Code: 
module mux(a,b,s,y);
input [63:0] a,b;
input s;
output [63:0] y;
reg [63:0] y;
always @(s)
case(s)
1'b0: y=a;
1'b1: y=b;
endcase
endmodule

your always should have both a and b in the sensitivity list or just use * instead of s.

I'm not sure why you created an addcc and an addccc you should just use your addc and tie off the cin when you don't need it and don't connect the co when you don't need it. I also noticed you might want to think about using something like this to code the carry in addition:
Code Verilog - [expand]
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wire [65:0] si;
assign si = {a,cin} + {b,cin};  // this guarantees a single adder in the design instead of two adders in series.
assign s = si[64:1];
assign co = si[65];


regards
 
Last edited:

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