I am designing a bandgap with ppm<10 and vref=2.5

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I have question. how to get 10ppm TC after trimmed for vref accuracy due to process variation ?
 

Hi Tpeng.

I didnt understand your question. Please, could you clarify?
You need to properly design your circuit and use layout techniques to reduce the impact of variability. Moreover, you can add a trim circuit (For instance, PTAT Resistor) that permits you to adjust the PTAT voltage summed with the VBE voltage. In this way, after trimming you can achieve 10 ppm/C.
That is... the trimming circuit will mitigate the impact of process variation.
 

palmeiras,
thank your reply.
my question is from my old projects last year. after trimming, the accurency of every part is in SPEC, but the TC is different each other.
I know your mean that by adding more trim circuit , it is possible to get every part has accurency (eg. 1%) and 10ppm/C.
 

Hi tpeng,

If I undertood well your question, the temperature coefficient of your samples after trimming are different, although the circuit achieved the accuracy needed.
This phenomenon can happen for two reasons:
1) Maybe you need to add more bits in your trim circuit, to guarantee a better temperature coefficient.
2) However, some non-idealities cannot be perfectly compensated using the traditional linear PTAT Trimming. Examples of them are: package shift, Early voltage, Temperature coefficient of resistors. When the impact of these errors on temperature performance is not linear, you may have samples with different TC even with more trim bits added. Did you understand what I´m mean?! Nevertheless I think you can achieve 10 ppm/C as you wish.
 
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    tpeng

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Palmaeiras,
your reply is useful for me. Thank you. I think that add more bits for tranditional linear PTAT trimming for better TC will be my next action item.
 

palmeiras said:
Can you upload this figure?
How much is this difference? In terms of mV, uV? Small difference is expected.
Click to expand...

my test results as follows,

-40 (degree) 2.848(V)
-30 2.68
-20 2.531
-10 2.38
0 2.28
10 2.223
20 2.213
30 2.203
40 2.199
50 2.194
60 2.19
70 2.185
80 2.18
90 2.174
100 2.169
110 2.162
120 2.156
 

tpeng said:
Palmaeiras,
your reply is useful for me. Thank you. I think that add more bits for tranditional linear PTAT trimming for better TC will be my next action item.
Click to expand...

Hi Tpeng,

I hope it works. By the way, are you trying to trim only one resistor? What is the topology of your BGR? if you wish, you can upload the figure and we can discuss more about it.

---------- Post added at 15:26 ---------- Previous post was at 15:07 ----------
Hi Samuel,

I see. An output voltage variation of 650 mV between T(-40) and T(40) is not expected.
Is this data result of simulation? In simulation we expected an output voltage variation less than 10 mV in this temperature range.
I could say that an output voltage variation of 50 mV between T(40) and T(120) can happen depending on your conditions (corners, monte carlo simulation, VDD, and so on).
But the behavior of your circuit in low temperatures is not expected.
Are you sure that all transistors are in saturation @-40C?
you need to check the operation (e. g. diode behavior) in this temperature value too.
Does your bandgap implements Banba architecture?
 



Hi，palmeiras

the designed chip had been tapeout， the above results are not simulation data but test data。
the architecture of bandgap is Banba。

I feel that the variations are obvious in lower temperature , why? I remember I have simulated that from -40 to 80, it is ok.
 

Hi samuel,

But you simulated it using corner and Monte Carlo models?
How many samples have you measured?
Take a look in this topic:



We have discussed possible reasons for such variations.

In your case, it is clear that the wrong operation only happens in low temperatures. I think that there are transistor in linear region.
 

palmeiras


hi, palmeiras
in the course of designing the bandgap chip, I had simulated that from -40 to 80in dc scan means, the simulated results shows ok.

thanks anyway. palmeiras
 

Palmaeiras,
my BGR topology is follow. it is only trim R2.


BG output of last circuit after trim like the follow:


if in corner simulation, the TC will show worse.
So I feel difficult to trim for TC when process variation.
 
Last edited:

Hi tpeng,
How are you implementing your trimmable resistor? Are the switches only simple transistors?
If yes, have you designed it with small on-resistance? Are they with high values of transistor length?
Regards,
 

Hi, palmeiras,
transfer gate is used as switch. Yes, its on-resistor less than LSB trim resistor.
By the way, another deisgn is that trim is simply by metal fuse with BOA pad, but less trim bit.
 

I had run a DC simulation and do a temperature sweep. I got a graph of Vref against temperature. After which I use the DERIV function in the calculator and another graph which is the derivative of the first appears.

how do you exactly measure TC in ppm/oC from temp range of 0 to 100oC for example.
 

TC = (1/ VREF (@ 27 C)) * (delta_VREF / delta TEMP)

Where VREF = output voltage at 27 degrees,
delta_VREF = the output variation (VREF maximum - VREF minimum) in the temperature range
delta_TEMP = temperature 1 (where VREF is maximum) - temperature 2 (where VREF is minimum). Usually, you design the point with derivative equal to zero in the middle of the temperature range, for instance, 50 degrees. Therefore, delta_TEMP in this case is 50 degrees.

Regards,
 

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