"SRAM cell 6T
.LIB "ptm_16nm.lib" predictive_16_lp
.LIB "ptm_32nm.lib" predictive_32_lp
.lib ".\Libraries\ptm_16nm.lib" predictive_16_lp
.lib ".\Libraries\ptm_16nm.lib" predictive_16_hp
.lib ".\Libraries\ptm_22nm.lib" predictive_22_lp
.lib ".\Libraries\ptm_22nm.lib" predictive_22_hp
.lib ".\Libraries\ptm_32nm.lib" predictive_32_lp
.lib ".\Libraries\ptm_32nm.lib" predictive_32_hp
**mos transistors - latch
m1 Q QR 0 0 nmos_22nm_hp w=88n l=22n
m2 Q QR 1 0 nmos_22nm_hp w=88n l=22n
m3 QR Q 0 1 pmos_22nm_hp w=33n l=33n
m4 QR Q 1 1 pmos_22nm_hp w=33n l=33n
**mos transistors - data access
m5 BL wl Q nmos_22nm_hp w=44n l=22n
m6 BLR wl QR nmos_22nm_hp w=44n l=22n
.param pulse_period = 50ns
.param pulse_width = 4ns
.param pulse_delay = 2ns
.param pulse_rise = 100ps
.param pulse_fall = 100ps
*sources supply
vdd 1 0 dc 0.95
** access control
vwl wl 0 pulse(0 0.95 pulse_delay pulse_rise pulse_fall pulse_width pulse_period)
**data
vbl BLR1 0 dc 0.95
vblr BL1 0 pulse(0.95 0 pulse_delay pulse_rise pulse_fall pulse_width pulse_period)
**control
vr_w r_w 0 pulse(0 0.95 pulse_delay pulse_rise pulse_fall pulse_width pulse_period)
*devices switches
GBL BLR1 BL VCR PWL(1) r_w, 0 0v, 1e20 0.95v, 1.00000E-20
GBLR BL1 BLR VCR PWL(1) r_w, 0 0v, 1e20 0.95v, 1.00000E-20
*analysis
.tran 0.01n 50n start = 0
*.print tran v(BL) V(BLR)
.option post
.end
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