Hspice oscillation issues in LDO design

[jutek]

hello

i met this strange results.

I thought it is stability problem but not, phase margin is 70deg.

So what can be a reason of this oscillations?

my hspice opions:

.options post nomod
+RELTOL=0.01 ITL4=100 ABSTOL=1n VNTOL=1e-4 DVDT=4
+ITL5=0 CSHUNT=1e-15 DVDT=4
+MAXORD=2 LVLTIM=1 TRTOL=25
+accurate=1 method=gear
+ ABSMOS=1e-9 ABSVDC=1e-6 ABSV=1e-6 CHGTOL=1e-14 DEFAD=5.29e-12 +DEFAS=5.29e-12 DEFNRD=0.1 DEFNRS=0.1 DEFPD=9.2e-06 DEFPS=9.2e-06 +TNOM=27

but even without this options it happens

Analysis declaration: .TRAN 0.01US 50u

if i use 0.1u step it looks ok, but the plot is not accurate as it should be

Thanks for any help

regards

 

[hr_rezaee]

hspice error (?)

Hi
what is your circuit.
regards

 

[jutek]

Re: hspice error (?)

Hi
what is your circuit.
regards

hi

it's an adjustable LDO, so i think it shouldn't be a problem in the simulation.

i met it first time

 

[hr_rezaee]

hspice error (?)

Hi
what is LDO?
regards

 

[elantra]

Re: hspice error (?)

it should be an unstable circuit. for ldos, stability issues are widely discussed.
take a look at your gain margin.
also, you can change your output cap and its esr to resimulate.


good luck.

Added after 1 minutes:

normally i use 10ns or less for my maximum step to get more accurate result.
for your reference.

 

[electronrancher]

hspice error (?)

it doesn't seem stable. if you are using an ideal ouput cap, try putting some small series resistance to model the ESR, like 30mOhm. That will give a zero and perhaps cure the oscillation.

Did you run AC sims at both of these points? Is there any chance that the gain peaks back above 0 at some later frequency where the phase is negative? This kind of thing is called conditional stability, and often a step can push a circuit over into the other gain region, giving an oscillation in a circuit that looked to have good phase margin at the first gain=0 point.

 

[jutek]

Re: hspice error (?)

it doesn't seem stable. if you are using an ideal ouput cap, try putting some small series resistance to model the ESR, like 30mOhm. That will give a zero and perhaps cure the oscillation.

Did you run AC sims at both of these points? Is there any chance that the gain peaks back above 0 at some later frequency where the phase is negative? This kind of thing is called conditional stability, and often a step can push a circuit over into the other gain region, giving an oscillation in a circuit that looked to have good phase margin at the first gain=0 point.

i use ESR 0.1Ohm. I've checked two cases in AC simulation and everything is ok.

The picture is for 10ns transient step. For 100ns step simulation is ok

 

[electronrancher]

hspice error (?)

wait - so is it working with ESR, or the problem still exists?

i usually also avoid gear integration method as it can hide or produce funny stuff. i knew of some designers who changed their bandgap simulations to gear to hide the fact that the sim showed oscillation! guess what happened when the chips came out? oscillation!

 

[nuiscet]

hspice error (?)

the set of accurate=1 may cause the oscillation sometimes.

 

[andy2000a]

hspice error (?)

for LDo design , you should know dynamic load test
and Ti have some paper talk about
"fast response LDO"

hspice 2005 have a bug in .probe tran cap(xx)
in tran sim "cap(xx)" will abort yhe simulation and no error list ,

use .print cap(xx) is ok

but .dc .ac is OK

 

[jutek]

Re: hspice error (?)

the set of accurate=1 may cause the oscillation sometimes.

nuiscet and electronrancher are right

if i comment accurate=1 and change method to default strange oscillations dissapear.

thanks

regards

 

[joskin]

Re: hspice error (?)

hello

i met this strange results.

I thought it is stability problem but not, phase margin is 70deg.

So what can be a reason of this oscillations?

my hspice opions:

.options post nomod
+RELTOL=0.01 ITL4=100 ABSTOL=1n VNTOL=1e-4 DVDT=4
+ITL5=0 CSHUNT=1e-15 DVDT=4
+MAXORD=2 LVLTIM=1 TRTOL=25
+accurate=1 method=gear
+ ABSMOS=1e-9 ABSVDC=1e-6 ABSV=1e-6 CHGTOL=1e-14 DEFAD=5.29e-12 +DEFAS=5.29e-12 DEFNRD=0.1 DEFNRS=0.1 DEFPD=9.2e-06 DEFPS=9.2e-06 +TNOM=27

but even without this options it happens

Analysis declaration: .TRAN 0.01US 50u

if i use 0.1u step it looks ok, but the plot is not accurate as it should be

Thanks for any help

regards

I think it's a stability problem. Although you said the PM is 70, perhaps the setup is something wrong when running simualtion.

 

[stoned]

Re: hspice error (?)

hi

it's not the circuit problem, ascribe to algebraic! I met this just some time ago
using .option method=gear can do it
the following copied from hspice manual

One limitation of the trapezoidal algorithm is that it can result in computational
oscillation—that is, an oscillation caused by the trapezoidal algorithm and not
by the circuit design. This also produces an unusually long simulation time.
When this occurs in circuits that are inductive in nature, such as switching
regulators, use the GEAR algorithm.

best regards
stoned

 

[rehty]

Re: hspice error (?)

phase margin is small signal stability analyse,
you should check your large signal condition.