hspice issue"timestep too small"

[Tiiu]

.options cshunt=1e-13

when I simulate,the report says "timestep too small".
one suspicious warning is because I connected all nodes of one transistor together.
how should I deal with this?

thanks in advance!

 

[wjlzhx]

hspice gshunt ramping

i think you have convergence
when i do the simulate with tran i got the problem too
you can see the hspice help

 

[gharuda]

timestep too small trouble with node

did u connect source, drain and gate to one node.

 

[paulux]

site:www.edaboard.com tran option trap

Sometimes due to model non-convergence....but this could be improved if use Hspice 2006 version.....

 

[paladinzlp]

spice timestep too small

hai Tiiu
(1)You can set options about convergence.
(2)Set some point's initial voltage
in a word, I think that is a convergece problem.

Perhaps that can help!

 

[Tiiu]

interal timestep too small

Thanks to all
I had added the initial voltages for the circuit and tried some spice options like:convergence=-1 dcon=1 BYPASS=1 CSHUNT=1 dvdt=0

but it doesn't help

what value I should assign to RELMOS,ABSMOS,DVDT and LVLTIM to get a better convergence?

 

[harrytrinh]

cshunt hspice

Hi,
1. You could add:" .option gshunt=1e-14 and cshunt=1e-14" into the top of sim file. It coukd be useful
2. If it doesn't help, You can look at in the list file (at the end of list file) then see the point that spice announce timestep too small. You could find some thing relative convergence problem, forexample, you have some devices (as fuses) that their nodes are connected togetther.

That is my way to solve the problem that sometimes I got. Good luck!

 

[Tiiu]

timestep too small spice

Hi,
1. You could add:" .option gshunt=1e-14 and cshunt=1e-14" into the top of sim file. It coukd be useful
2. If it doesn't help, You can look at in the list file (at the end of list file) then see the point that spice announce timestep too small. You could find some thing relative convergence problem, forexample, you have some devices (as fuses) that their nodes are connected togetther.

That is my way to solve the problem that sometimes I got. Good luck!

hi harrytrinh,
I added the ".option gshunt=1e-14 and cshunt=1e-14"but it doesn't help.
meantime I found 3 nodes claiming non-convergence at the lis file.
Acctually these 3 nodes are the voltage sources within package model.
and yes,there are many devices whose nodes are connected together,but those devices are right be they should,I can't change them.
How should I deal with them?

 

[harrytrinh]

I don't knot about that package model. But if you can remove that voltage source the problem will go away.

 

[simonkuo]

If you add the package model, try to add a small resistor in your power rail , say 1 ohm or 2 ohm, to decrease the Q factor of L of package model. Thease small resistor can be modeled as your metal line resistance, I thank that will not affect your ciecuit simulation accuracy and help your circuits convergence.

 

[wanily1983]

the non-convergency is a very "irksome" problem, when i simulate the whole circuit system, i encount this problem. who have a detailed experience to share about this?

 

[manissri]

use gmindc and other option to remove the convergance problem

 

[Vamsi Mocherla]

Hey try and see if you are trying to ramp up your voltage sources too fast. Internal time step algorithm is used by HSPICE to extrapolate to the next voltage or current. If there is a sudden ramp in the voltage or current in any node, then it will give an internal timestep error.

Rather than changing GMINDC and G/C-SHUNT (which are used in high-frequency) try and type METHOD=GEAR. I think that GEAR method solves better than TRAP(trapezoidal).

I hope that it helps.

 

[ubetimcool]

In your spice file, just add this..

.OPTIONS
+itl4=100

This works.

 

[Tiiu]

Thanks to all!!!
The issue is sloved by change ".option csdf "to ".option post" and add a statement ".option dcstep=1e-9"