saied_157
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Hello everyone
I want to find gate leakage current in 45nm cmos model. I have found some sample for calculating leakage current but they are not work correctly.
Here is my code:
spice deck
.inc '../NMOS_VTL.inc'
.inc '../PMOS_VTL.inc'
.inc 'AND2_X1.sp'
vcc 1 0 1
v1 vs 0 1
v2 vd 0 0
X1 vs vs out 1 vd AND2_X1
c1 0 out 1p
.tran 1ns 400ns
.measure igate ***
.end
I want to know what should I have put instead of *** to calculate leakage current?
Thanks in advance
I want to find gate leakage current in 45nm cmos model. I have found some sample for calculating leakage current but they are not work correctly.
Here is my code:
spice deck
.inc '../NMOS_VTL.inc'
.inc '../PMOS_VTL.inc'
.inc 'AND2_X1.sp'
vcc 1 0 1
v1 vs 0 1
v2 vd 0 0
X1 vs vs out 1 vd AND2_X1
c1 0 out 1p
.tran 1ns 400ns
.measure igate ***
.end
I want to know what should I have put instead of *** to calculate leakage current?
Thanks in advance