How would you drive a 5V, 120MHz square wave into 200pF?

So I've been building current mode class D RF amps lately (around 123MHz). Up until now I've been using class E preamps to drive a rough sine wave into those FETs, which works all right, but I know that a square wave would work better. But I haven't thought of a convincing method of producing such a gate drive (without making a custom ASIC anyways). I'm looking for rise/fall times of 3ns or less, no excessive ringing (peak gate voltage must not exceed 6V), and with overall efficiency of 25% or so (about 1W per gate). My starting signal source can be a +10dBm carrier (sine wave) from a 50ohm port, or a 10mA CML clock.

I've been trying things in SPICE, including BJT and MOS push-pull drivers. What I'm finding is that in order to build a fast enough driver stage, I need devices large enough that the input capacitance of the driver is still quite significant, and requires large peak currents to operate properly (like 0.5A or more). So to get from my starting carrier, I would need several driver stages cascaded, and that's just going to be a mess on a PCB...

Here's an example of one of the better looking circuits I've come up with (I've found that simplicity works best so far...), using Nmos FETs on the output (meaning I'd need complementary drive signals, with some DC biasing). But even this requires large peak currents from my pulse sources, and I can't come up with a good way to get that from my available signal source.



I was also looking at the possibility of just using a bunch of logic inverters/buffers in parallel, but it seems like the only devices specified for very high speed and drive strength aren't capable of giving near 5V output swing (most are ECL or LVDS transceiver ICs).

Any ideas for me?

Have you looked at high speed CMOS logic such as these for use in parallel?

Edit: Also here are some logic-level MOSFETs that operate down to 2.5V input.

No I hadn't heard of those specific logic families. But their specs look practically identical to similar devices in the AHC/AHCT families.
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All of them spec a delay of ~5ns when loaded with 50pF.

Not that those specs are bad or anything. They might be able to do it with 4-8 gates in parallel, so I'll likely give that a try.

The other issue is how I interface my low-amplitude carrier/clock to the gate inputs. A high speed comparator would be ideal, but all comparators that are fast enough seem to have outputs that aren't compatible with 5V CMOS.