How would i decrease the clock frequency

[wylll]

if i have a clock frequency of 50M Hz, how would i decrease the frequency to 10k Hz?

 

[barry]

How about some context? FPGA? Microprocessor? Basically, you need to divide your signal by 5000.

 

[wwfeldman]

depends

note added after the fact:
sorry
i missed the change from M to k

if you are building a circuit with of the shelf components, you can use a 74390 TTL bi-quinary counter
it has a divide by 5 section and a divide by 2 section
the divide by 5 section would do the job

if you are programming this into a programmable logic device, you can likely do the equivalent,
but you may have to design the divide by 5 yourself
use teh TI data sheet on '390 as a guide

if you are programming this into a processor in VHDL, Verilog, C, python or some other programming language,
you can do a similar thing in software, but someone else will have to give you coding guidance
i'm still learning some of those languages

if you are programming this into a processor, you may be able to use the processor's built in
clock generation process, which is processor specific and should be covered in the documentation

 

[KlausST]

Hi,

Run a counter: 0 to 2499. On every overflow/reset toggle the output.

Klaus

 

[Akanimo]

Hi,

You need an n-bit counter (i.e. 2^n - 1 is greater than or equal to the number of counts that you want minus 1). In your case, since 2^12 - 1 = 4095 (which is not enough to count up to 5000 - 1 = 4999) and 2^13 -1 = 8191 (which is greater than 5000 - 1 = 4999), then 13 bits will be chosen for the counter.

Take the output (the 10kHz clock) from the output of the MSB flipflop. Since this counter can count beyond 5000 - 1 = 4999 which should be your maximum, you'll have to reset the counter in the 'next' rising edge of the 50MHz clock after the output is decimal 4999 or binary 1001110000111. The input signal to the counter here will be your 50MHz clock.

Realize that you have to design the counter to overcome propagation delay.

 

[KlausST]

Hi,

Akanimo's solution is correct but gives about 2% duty cycle.

The solution of post#4 needs identical ressources but gives perfect 50% duty cycle.

Klaus

 

[Akanimo]

Hi Klaus,

I don't seem to understand how my solution would give 2% duty cycle. Can you explain please?

- - - Updated - - -

(4999 - 4095)/5000 = 0.18 = 18% duty cycle. That is 0.18*1/10000Hz = 18us for the generated clock to be high.

 

[Akanimo]

The Si5351 from Silicon Labs is a Low-cost PLL IC just incase you are designing on the board level.

 

[KlausST]

Hi,

I don't seem to understand how my solution would give 2% duty cycle. Can you explain please?

My calculation was wrong. Not 2% but your 18% duty cycle is correct.
Sorry.

Klaus