babaduredi
Member level 1
Hi,
We have two scenarios:
module dff_blocking(d, clk, q)
input d,clk;
output q;
reg q,q1;
always@(posedge clk)
begin
q=d;
q1=q;
end
endmodule
and another one with non-blocking
module dff_nonblocking(d, clk, q)
input d,clk;
output q;
reg q,q1;
always@(posedge clk)
begin
q<=d;
q1<=q;
end
endmodule
How will the hardware look like in both cases post synthesis? second one looks simple but i don't have idea for first one.
We have two scenarios:
module dff_blocking(d, clk, q)
input d,clk;
output q;
reg q,q1;
always@(posedge clk)
begin
q=d;
q1=q;
end
endmodule
and another one with non-blocking
module dff_nonblocking(d, clk, q)
input d,clk;
output q;
reg q,q1;
always@(posedge clk)
begin
q<=d;
q1<=q;
end
endmodule
How will the hardware look like in both cases post synthesis? second one looks simple but i don't have idea for first one.