How was the verilog-A language simulated ?

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Muthuraja.M

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Hi friends,

Verilog HDL is simulated by modelsim and synthesized by xilinx.

Is verilog-A language is simulated using modelsim ?

If no which software is used to simulate the verilog-A language ?

Reply me.


Thanks in advance...
 

ok fine.

i am having modelsim 6.3gp1 version. By using this can we simulate the verilog-A language.
 

Is there is any student version for Questa ADMS to download...
 

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