How use Verig A to generate clock jitter in cadence spectre

[chungming]

jitter modeling in spectre

As title~~
I want simulate a sigma delta ADC with clock jitter.
someone tell me use verilog A to generate it , but he didn't say how to do.
Is anyone can help me what i should do in cadence spectre?

 

[tsb_nph]

verilog, generate clock

As title~~
I want simulate a sigma delta ADC with clock jitter.
someone tell me use verilog A to generate it , but he didn't say how to do.
Is anyone can help me what i should do in cadence spectre?

Verilog-A clock model with and without jitter
https://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.va

Other verilog-A models
https://www.designers-guide.org/VerilogAMS/index.html

Document describing the model (Section 7.3)

https://www.designers-guide.org/Analysis/PLLjitter.pdf

 

[chungming]

jitter modeling cadence

thanks for your help~!
But i am first time to simulate with jitter.
Where should i add it?Is directly add with sampling(input) clock ?

thanks~~!