Jul 12, 2011 #1 C cysco Newbie level 5 Joined Jul 27, 2009 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,325 In verilog, I can write like this: assign next_lookup = lookup[15:0] & {16{lookup_en}} // lookup_en is 1 bit. How to have the same statement in VHDL??
In verilog, I can write like this: assign next_lookup = lookup[15:0] & {16{lookup_en}} // lookup_en is 1 bit. How to have the same statement in VHDL??
Jul 12, 2011 #2 R rca Advanced Member level 5 Joined May 20, 2010 Messages 1,527 Helped 355 Reputation 710 Reaction score 336 Trophy points 1,363 Location Marin Activity points 8,773 one way: FOR i IN 0 TO 15 GENERATE BEGIN next_lookup <= lookup AND lookup_en; END GENERATE; ---------- Post added at 10:57 ---------- Previous post was at 10:54 ---------- an other way: SIGNAL vect_lookup_en : STD_LOGIC_VECTOR(15 DOWNTO 0); vect_lookup_en <= (OTHERS=>lookup_en); next_lookup <= lookup AND vect_lookup_en;
one way: FOR i IN 0 TO 15 GENERATE BEGIN next_lookup <= lookup AND lookup_en; END GENERATE; ---------- Post added at 10:57 ---------- Previous post was at 10:54 ---------- an other way: SIGNAL vect_lookup_en : STD_LOGIC_VECTOR(15 DOWNTO 0); vect_lookup_en <= (OTHERS=>lookup_en); next_lookup <= lookup AND vect_lookup_en;