how to Write verilog for selecting part of bus

Dear all,

There are bus A[0:100] ,B[0:15], and the register length[3:0].
The register length can be set by user.
If the length = 0, the B[0:15] = A[0:15],
If the length = 1, the B[0:15] = A[1:16],
If the length = 2, the B[0:15] = A[2:17],
If the length = 3, the B[0:15] = A[3:18], and so on.

can I write like this,
assign s_point = length;
assign e_point = length + 15;
assign B[0:15] = A[s_point:e_point];

The best method is the following method?

always@(length or A) begin
case(length)
0 : B[0:15] = A[0:15];
1 : B[0:15] = A[1:15];
2 : B[0:15] = A[2:15];
...
15 : B[0:15] = A[15:30];
endcase
end

Does there have any good method to write??

Thanks!!

no ,u make a mistake !

Hi,
Not in plain verilog. But in SystemVerilog, you can do:



I know VCS supports this part of SV already.

HTH,
Aji
http://www.noveldv.com

I am sorry! I only want to know how to write it in verilog!

I believe that the optimal way is

always@(length or A) begin
case(length)
0 : B[0:15] = A[0:15];
1 : B[0:15] = A[1:15];
2 : B[0:15] = A[2:15];
...
15 : B[0:15] = A[15:30];
endcase
end

yes. I think only the second method is a good method.