How to write Verilog code for MBE multiplier

[kuankuan]

Hi,
I am new to verilog. I need to write verilog code for modified booth multiplier. How to write the code for padding 1 zero to LSB of a multiplier, let's say 4bits input?
Thanks.
Rgds,
KK

 

[tariq786]

see how concatenation works in verilog

assign padded = {input,1'b0} //if padded is 5 bits

 

[kuankuan]

Thanks! I got it already.

another question:
If I have a 7bits multiplier, (let's say 0010110), how do I write verilog code to check for the bits in overlapping group of 3, such as (starting from lsb 110, then 101, then 001)? Assuming I do not know what is the actual multiplier number but I can fix it to 7 bits. I know I need to use LOOP but do not know exactly how to use the loop to check on the increasing iteration.