vijaymarine
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module bidir(dio,clk,rst);
input clk,rst;
inout [15:0]dio;
wire [15:0]dout;
wire oe;
reg [15:0]inreg;
assign dio=oe? dout:16'hzzzz;
always @(posedge clk)
if(rst)
inreg<=16'h0000;
else
inreg<=dio;
endmodule
input clk,rst;
inout [15:0]dio;
wire [15:0]dout;
wire oe;
reg [15:0]inreg;
assign dio=oe? dout:16'hzzzz;
always @(posedge clk)
if(rst)
inreg<=16'h0000;
else
inreg<=dio;
endmodule