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how to write the second argument of $fsdbDumpvars() in verilog & VHDL mixed project
hi,
my project is verilog and VHDL mixed. top module and testbench are verilog, and all submodule is VHDL.
now i want to dump fsdb file only for certain submodule, not for the whole hierarchy.
i know if the project verilog only. i can use task like this:
but how to write this task, when VHDL is mixed in?
thanks !
hi,
my project is verilog and VHDL mixed. top module and testbench are verilog, and all submodule is VHDL.
now i want to dump fsdb file only for certain submodule, not for the whole hierarchy.
i know if the project verilog only. i can use task like this:
Code:
$fsdbDumpvars(0,tb.top.submodule1.signal1);but how to write this task, when VHDL is mixed in?
thanks !