How to write test code?

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sheikh

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Hello Dears
I designed a unit and now want to test it by using an external file (a file in my computer) as input. I need to read the elements of this file at specific times (for instance, every 8 clock pulse, read new inputs from the file (like reading from external RAM)). I don't know how can i do it by a vhdl code. Could you please tell me how to do it?
Regards
Mostafa
 

I presume you are familiar with the general concept of test benches. You should also know that test benches can generate arbitrary timed stimulus sequences, either using the system clock supplied to the design under test or additional timed test bench statements. If my assumption is correct, the only remaining problem is how to use data read from external files as stimulus.

I suggest to take a look at the text_io package. The purpose of it's procedures is more or less self explanatory, otherwise you can expect examples in the simualtor documentation.
 
Hi, I have a sample read code whic h I implemented.. You can use it as reference...
and you migh have to use a conter to read after every 8 clocks...

Code: 
 process(rxclkdiv)
     file   infile1       : text open read_mode is  "..\..\..\source\sim\txpath_data.txt";   --declare input file
     variable  inline1    : line; 
     variable  dataread1 : string(17 downto 1);
     variable j : integer := 0;
     variable char : character:='0'; 
     variable end_read : std_logic := '0';
 begin
   if(rising_edge(rxclkdiv))then
   if(end_read = '0') then
     if (not endfile(infile1)and start_tx_read='1') then   
       readline(infile1, inline1);       
       read(inline1, dataread1);

       for j in 10 to 17 loop        
         char := dataread1(j);
         ddr_address1((j-10)*4 + 3 downto (j-10)*4) <= f_char2hex(char);
       end loop;  
        
       for j in 5 to 8 loop        
         char := dataread1(j);
         ddr_burst_size1((j-5)*4 + 3 downto (j-5)*4) <= f_char2hex(char);
       end loop; 
 
       if(dataread1(1) = '0') then
         ddr_first_burst1 <= '0';
       else
         ddr_first_burst1 <= '1';
       end if;  
         
       if(dataread1(3) = '0') then
         ddr_command_valid1 <= '0';
       else
         ddr_command_valid1 <= '1';
       end if;  
       
       ddr_address2 <= (others => '0');
       ddr_burst_size2 <= (others => '0');
       ddr_command_valid2 <= '0';
       ddr_first_burst2 <= '0';
       
     elsif(endfile(infile1)) then
         file_close(infile1);
         ddr_command_valid1 <= '0';
         ddr_command_valid2 <= '0';
         end_read := '1';  
     end if;
   else
    ddr_command_valid1 <= '0';
    ddr_command_valid2 <= '0';  
   end if;
   end if;  
 end process ;
 
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    sheikh

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Thanks dears
now I want to write a code to read three inputs from three different files and then send them to a UUT ( unit under test ) and save the results in another file. i wrote the following code but i don't know why it doesn't produce any out put? Could you please tell me your opinion.
Regards
Mostafa

Code: 
LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.all;

ENTITY E_testbench IS
END E_testbench;

ARCHITECTURE behavior OF E_testbench IS 

-- Component Declaration

Component E_UNIT
                      port(
	                        CLK               : in  STD_LOGIC;                    
	                        CLR               : in  STD_LOGIC;                    
	                        A                 : in  STD_LOGIC_VECTOR(31 downto 0);    
	                        B                 : in  STD_LOGIC_VECTOR(31 downto 0);  
	                        C                 : in  STD_LOGIC_VECTOR(31 downto 0);  
                            Start             : in  STD_LOGIC;
	                        EE                : out  STD_LOGIC_VECTOR(31 downto 0)
                          );
End Component ;

--period of clock,bit for indicating end of file.
signal clk,endoffile, CLR                        : Std_logic := '0';
signal Start                                     : Std_logic ;

--data read from the file.
signal    dataread_A                             : Std_logic_vector(31 downto 0);
signal    dataread_B                             : Std_logic_vector(31 downto 0);
signal    dataread_C                             : Std_logic_vector(31 downto 0);

--data to be saved into the output file.
signal    EE_Val                                : Std_logic_vector(31 downto 0);

--line number of the file read or written.
signal    linenumber                            : integer:=1;

   -- Clock period definitions
constant CLK_period                             : time := 10 ns;

begin

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;


--read process
reading : process

                 file      infile_A    : text is in  "C:\Users\Mostafa\Downloads\TEST\A.txt";           --declare input file_A
                 file      infile_B    : text is in  "C:\Users\Mostafa\Downloads\TEST\B.txt";           --declare input file_B
                 file      infile_C    : text is in  "C:\Users\Mostafa\Downloads\TEST\C.txt";           --declare input file_C
                 variable  inline_A    : line;                                                          --line number declaration
                 variable  inline_B    : line;                                                          --line number declaration
                 variable  inline_C    : line;                                                          --line number declaration
                 variable  dataread_AA : Std_logic_vector(31 downto 0);
                 variable  dataread_BB : Std_logic_vector(31 downto 0);
                 variable  dataread_CC : Std_logic_vector(31 downto 0);
begin


        if  (clk = '1' and clk'event) then

        if ((not endfile(infile_A) and (not endfile(infile_B) and (not endfile(infile_C))))) then     

 --- Reading_A value       
         readline(infile_A, inline_A);                                    																				  
         read(inline_A, dataread_AA);
         dataread_A <=dataread_AA;   

 --- Reading_B value       
         readline(infile_B, inline_B);                                    																				  
         read(inline_B, dataread_BB);
         dataread_B <=dataread_BB; 
    
 --- Reading_C value       
         readline(infile_C, inline_C);                                    																				  
         read(inline_C, dataread_CC);
         dataread_C <= dataread_CC; 	

        else
          endoffile <='1';                          
       end if;
	   end if;
	   
end process reading;

-- Send to Unit Under Test

UUT         : E_UNIT Port Map
			     ( CLK => clk, CLR => CLR, A => dataread_A  , B => dataread_B  , C => dataread_C   , 
					 Start => start, EE => EE_Val
				   );



-- write process

writing : process
                 file      outfile  : text is out "C:\Users\Mostafa\Downloads\TEST\EE.txt";  
                 variable  outline  : line;                     
              begin
                if ( clk = '0' and clk'event) then
                if(endoffile='0') then                          
                                                                 
                write(outline, EE_Val);
                writeline(outfile, outline);
                linenumber <= linenumber + 1;
                else
                  null;
                end if;
                end if;

          end process writing;
Start <= '1' , '0' after 10 ns;

end behavior;
 

your input process has no wait statements or sensitivity list. It will loop forever and probably freeze the simulation. The same for the output process.
 

Hello Dears
I wrote a vhdl code that read data from three different files and send them to an "uut" and save the results in another file. this code read the values correctly and in the "isim" i have the true waveform for output, but in the output file there isn't all results and i don't know why it happen.
about the code:
it read data every 13 clock pulse. also each input file contain three elements ( values).

Code: 
LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.all;

ENTITY READ_E_testbench IS
END READ_E_testbench;

ARCHITECTURE behavior OF READ_E_testbench IS 

  CONSTANT CLOCK_PERIOD    : TIME           := 10 ns;

Component Efm
                      port(
	                        CLK               : in  STD_LOGIC;                    
	                        CLR               : in  STD_LOGIC;                    
	                        a                 : in  STD_LOGIC_VECTOR(31 downto 0);    
	                        b                 : in  STD_LOGIC_VECTOR(31 downto 0);  
	                        c                 : in  STD_LOGIC_VECTOR(31 downto 0);  
                            Start             : in  STD_LOGIC;
	                        Efm               : out  STD_LOGIC_VECTOR(31 downto 0)
                          );
End Component ;

signal Clk, Clr: std_logic := '0';
signal Start   : std_logic;
Signal a, b, c : std_logic_vector (31 downto 0);
Signal Efm     : std_logic_vector (31 downto 0);

BEGIN

--- Start of Efm Calculation.
    
	Start <= '1', '0' after 10 ns; 



UUT         : Efm Port Map
			                                 ( CLK => clk, 
											   CLR => CLR, 
											   a => a, 
											   b => b, 
											   c => c, 
					                           Start => start,
											   Efm => Efm
				                              );

   ------------------------------------ clock simulator -----------------------------------
  clock : process
  begin
		CLOCK_LOOP : LOOP
		CLK <= transport '0';
		WAIT FOR CLOCK_PERIOD/2;
		CLK <= transport '1';
		WAIT FOR CLOCK_PERIOD/2;
		END LOOP CLOCK_LOOP;
  end process clock;
  
  
   ------------------------------- stimuli process ---------------------------------------
     tb : PROCESS
                 file      infile_a    : text; 
                 file      infile_b    : text;
                 file      infile_c    : text;
                 file      result_file : text;				 
  -----------------------------------------------------------------------     
    procedure write_result( Efm : in STD_LOGIC_VECTOR(31 downto 0)
                           ) is
      variable txt_out : LINE;
    begin
      file_open(result_file, "C:\Users\Mostafa\Downloads\TEST\Result.txt", append_mode); 
	  
      write(txt_out, Efm,right,0);
      writeline(result_file, txt_out);
      file_close(result_file);
    end write_result;  
  -----------------------------------------------------------------------     
-- Function for Reading a				 
    function read_data_a(file infile_a : TEXT) return STD_LOGIC_VECTOR is
      variable txt_a   : line;
      variable input_a : STD_LOGIC_VECTOR(31 downto 0);
    begin
      readline(infile_a,txt_a);
      read(txt_a, input_a);
      return input_a;
    end read_data_a;	  
  --------------------------------------------------------------------	    
-- Function for Reading b				 
    function read_data_b(file infile_b : TEXT) return STD_LOGIC_VECTOR is
      variable txt_b   : line;
      variable input_b : STD_LOGIC_VECTOR(31 downto 0);	  
    begin
      readline(infile_b,txt_b);
      read(txt_b, input_b);
      return input_b;
    end read_data_b;	  
  ----------------------------------------------------------------------  
-- Function for Reading c				 
    function read_data_c(file infile_c : TEXT) return STD_LOGIC_VECTOR is
      variable txt_c   : line;
      variable input_c : STD_LOGIC_VECTOR(31 downto 0);	  
    begin
      readline(infile_c,txt_c);
      read(txt_c, input_c);
      return input_c;
    end read_data_c;	  
  -----------------------------------------------------------------------   
  begin

    file_open(infile_a, "C:\Users\Mostafa\Downloads\TEST\a.txt", read_mode);
    file_open(infile_b, "C:\Users\Mostafa\Downloads\TEST\b.txt", read_mode);
    file_open(infile_c, "C:\Users\Mostafa\Downloads\TEST\c.txt", read_mode);

    for i in 0 to 2 loop
       a  <= read_data_a(infile_a); 
       b  <= read_data_b(infile_b); 
       c  <= read_data_c(infile_c); 
       wait for 13*CLOCK_PERIOD;	   
    end loop;
	
       wait for CLOCK_PERIOD;	
	   
    for i in 0 to 2  loop
      wait for CLOCK_PERIOD;	
      write_result(Efm);	
    end loop;	
	
    wait for 400*CLOCK_PERIOD;

    file_close(infile_a);	
    file_close(infile_b);	
    file_close(infile_c);
	
   end process;
end;

three outputs of unit under test (in the isim):


outputs that saved in the result file:
00000000000000010000100111111010
00000000000000010000100111111010
00000000000000010000100111111010

as you see the file just contain the second output.
Could you please help me to solve this problem.
Regards
Mostafa
 

At the time the file was written, the data was what was written. THis is where you need to debug the waveforms.
 

hey,

do post, if u get through the solution..
I like the improvisation u made from the reference ..

cheers
 

Re: How to solve my test bench code problem?

Thanks dear TrickyDicky
I have inputs and output at true clock pulse cycle in isim waveform. According to your comment, I found that my cod has problem at writing section. In fact it start to read the first input and wait for 13 clock and then read the second one and wait 13 clock and then read the third one (last value) and again wait for 13 clock ( this is an extra waiting while all inputs read before) then exit from loop, at this time the first output that obtain from first inputs changed and the second output released. So Could please tell me what can I do?

Also I send an image that show output waveform

First line is start, last line in output and others are inputs and the values that saved in output file is related to second out put ( missed the first output
Code: 
    for i in 0 to 2 loop
       a  <= read_data_a(infile_a); 
       b  <= read_data_b(infile_b); 
       c  <= read_data_c(infile_c); 
       wait for 13*CLOCK_PERIOD;	   
    end loop;
	
       wait for CLOCK_PERIOD;	
	   
    for i in 0 to 2  loop
      wait for CLOCK_PERIOD;	
      write_result(Efm);	
    end loop;
Regards
Mostafa
 
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