How to write psl in HDL file in Modelsim environment

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psl assertions in modelsim

The psl file can be simulated in the Modelsim(6.0), but how to
write psl assertions in HDL file.

I read the guide and it shows me like this:
// psl begin
// assert **
// end
------------
but when I "vlog" them, there is error message.

Who can show I the example code?
 

i know this reply is more than two years' late but i think it might help others

for making assertions in VHDL:

--psl property P1 is ..........;

--psl assert P1;

in Verilog:

//psl property P1 = ..........;

//psl assert P1;


u can have properties embedded in the HDL file or in a separate one
if they are embedded, there is nothing extra to write while simulating
 

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