how to write output in file (in veriliog)

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vinodh475

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i am writing one verilog code
my number is 128 bit number and it will generate different number in every clock cycle
so i need to write each and every number in a file
can u please help me how can i do that?
 

vinodh475 said:
can u please help me how can i do that?
Click to expand...
Since I also don't know how to perform a google search using the terms verilog file output I can't help you.
 

Hi Vinod,
First open file using $fopen task in an initial block.
Then you can use $fdisplay task. Let's assume your number changes on rising edge of the clock, then I would read its value on falling edge
always @(negedge clk)
$fdisplay(fid1,"%d", theNumber);
Before ending simulation you'll need to close the file ID.

Start doing, debugging errors you will learn better, then using ready code.

Good luck!
 

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Go ogle a google? I am confused now.

Other than my increased level of confusion, seriously, try using google sometimes. This one is no worse than some other complacent posts on this forum, but sometimes ... Just for the fun of it I just did a cut & paste of "how to write output in file (in veriliog)" into google, and even that turns up pretty relevant answers.
 

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