[SOLVED] how to write multi line macro in verilog

[hulk789]

`define print(v)\ 
$display("var v=%h",v)

module try();
reg [3:0] test1=4'b1111;
initial begin
  `print(test1);
end
endmodule

The above code is valid in system verilog but in verilog it will give the error
$display("var v=%h",v)
|
ncvlog: *E,EXPMPA (1.v,2|7): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
`print(test1);
|
ncvlog: *E,NOTSTT (1.v,7|15): expecting a statement [9(IEEE)].
module worklib.try:v
errors: 1, warnings: 0

 

[dave_59]

The problem is you have a space after the \, so you are escaping the space, not the newline.

This should be an error regardless of Verilog or SystemVerilog.